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IEEE International Conference on Communications (ICC)

作者： H.K. Chow A. Leon-Garcia Network Architecture Laboratory Department of Electrical & Computer Engineering University of Toronto ONT Canada

This paper proposes an approach to support integrated services Internet with RSVP over ATM shortcuts (ISAC). While similar to other LP switching approaches, our work is different in three major aspects. First, it focuses on supporting the integrated services model whereas other approaches currently support only best effort traffic. Second, our architecture adopts RSVP as the major signaling protocol and eliminates duplication of functionality in the ATM domain. Finally, while heterogeneous multicast has not yet been supported in any other approaches, it is considered in our proposal. Our design strives to achieve three fundamental objectives: (1) ensuring compatibility with existing networking standards, applications and system software, (2) maintaining data path efficiency, and (3) assuring portability for different operating system and switch control protocol. Our proposed architecture has been proven by a prototype implementation. Its operation has been verified by demonstrating a videoconferencing application. Our prototype has also been evaluated by measuring its signaling and control latency as well as the transfer delay of the data path.

关键词： Intserv networks Asynchronous transfer mode Application software Switches Software prototyping Prototypes Delay Web and internet services Traffic control Proposals

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Interactive workflows in a virtual laboratory for e-bioscience: The SigWin-detector tool for gene expression analysis

Interactive workflows in a virtual laboratory for e-bioscien...

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e-Science 2006 - 2nd IEEE International Conference on e-Science and Grid Computing

作者： Inda, Márcia A. Belloum, Adam S.Z. Roos, Marco Vasunin, Dmitry De Laat, Cees Hertzberger, L.O. Breit, Timo M. Integrative Bioinformatics Unit Faculty of Science University of Amsterdam Netherlands System Network and Engineering Group Faculty of Science University of Amsterdam Netherlands Computer Architecture and Programming Laboratory Group Faculty of Science University of Amsterdam Netherlands

ISBN: (纸本)0769527345

Explorative research is a vital part of biological sciences. Biologists frequently have to examine and compare multiple (large) sets of biological data in an interactive and explorative manner. Exploring alternative ways of examining the data and managing the necessary resources often require substantial (manual) effort and time. In this paper, we present a concrete example of how VLAM, a grid-based workflow management system, can enhance experimentation. We discuss in detail the process of developing the SigWin-detector, an application in the domain of bioinformatics. We show that SigWin-detector can promptly identify regions of increased gene expression in transcriptome maps and periodicity in weather data. We also show that the workflow can be extended or partially modified. The individual modules can also be used to compose different experiments. SigWin-detector fulfills the requirements of interactive and explorative experimentation. ©2006 IEEE.

关键词： Virtual reality

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VC-merge capable scheduler design

VC-merge capable scheduler design

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IEEE Workshop on ATM

作者： H.K. Chow A. Leon-Garcia Network Architecture Laboratory Department of Electrical & Computer Engineering University of Toronto Toronto ONT Canada

VC merging allows VC to be mapped onto the same VC label. It provides a scalable solution for network growth. It enables features such as stream merging in MPLS and RSVP wildcard filter to be efficiently supported over ATM. It also plays an important role in providing multipoint-to-multipoint multicast and share-tree multicasting paradigm. VC merging involves distinguishing cells from an identical merged VC label. Various approaches have been proposed to help this identification process. However, most of them incur additional buffering, protocol overhead and/or variable delay. They make the provision of QoS difficult to achieve. In this paper, we propose a novel merge-capable scheduler to support VC merging. The proposed scheduler consists of a core scheduler and a number of sub-queue sequencers forming a 2-level hierarchical structure. Using the proposed merge-capable scheduler, we can uniquely identify incoming cells while: (1) allowing cell cut-through forwarding and interleaving; (2) maintaining per-flow QoS; and (3) requiring no additional buffer and protocol overhead. We show analytically that the scheduler can guarantee a worst-case fairness and deliver a worst-case delay bound. We further analyze the scheduler performance in term of the service received by a queue and the average queuing delay experienced by a cell. The results indicate that the amount of services is fairly distributed among merging and non-merging flows according to their reservations. Moreover, the proposed merge-capable scheduler performs equally as well as its non-merging counterpart when reservations are highly utilized, even though it may introduce a minimal additional delay when utilization is low.

关键词： Switches Merging Virtual colonoscopy Filters Asynchronous transfer mode Delay Multiprotocol label switching Protocols Queueing analysis Proposals

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An energy-efficient bandwidth allocation method for single-chip heterogeneous processor 7

An energy-efficient bandwidth allocation method for single-c...

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7th International Green and Sustainable Computing Conference, IGSC 2016

作者： Zhu, Yatao Zhang, Shuai Ye, Xiaochun Wang, Da Tan, Xu Fan, Dongrui Zhang, Zhimin Li, Hongliang State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China School of Computer and Control Engineering University of Chinese Academy of Sciences Beijing China National Computer Network Emergency Response Technical Team/Coordination Center of China Beijing China State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi Jiangsu China

ISBN: (纸本)9781509051175

In recent years, many studies on optimization of energy consumption have focused on heterogeneous processor architectures. Heterogeneous computing model composed of CPU and GPU has developed from co-processing between the chips to CPU and GPU integration on the same die. On the one hand, because GPU can work under low voltage and ultra-low frequency, heterogeneous multi-core processors exhibit better energy efficiency compared to traditional CPU;On the other hand, because GPU usually has little or no shared cache, its memory bandwidth demand will be several times more than that of CPU for the same performance. Considering the constraints of power consumption and memory bandwidth, the contention problems of power and bandwidth among CPU and GPU in heterogeneous processor will inevitably occur. In this paper, energy-efficient bandwidth allocation method for heterogeneous processors allocates bandwidth to CPU and GPU and increases the overall throughput of CPU and GPU. Meanwhile the efficiency of energy consumption of heterogeneous processors is improved. The queuing delay is introduced to build a performance-energy model for heterogeneous processors. According to experience parameters, we analyze how the memory bandwidth allocation of off-chip affects the total throughput and energy efficiency. This paper also explores the change of performance-energy gains with the cache miss ratio of processors and the degree of scarce of available peak bandwidth. Based on the above research, the analytical solution of energy-efficient bandwidth allocation for optimal performance is obtained, and the solution can get more performance-energy gains compared with natural bandwidth allocation. © 2016 IEEE.

关键词： Bandwidth

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Data cache prefetching design space exploration for BlueGene/L supercomputer

Data cache prefetching design space exploration for BlueGene...

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17th International Symposium on computer architecture and High Performance Computing, SBAC-PAD 2005

作者： Brunheroto, José R. Salapura, Valentina Redígolo, Fernando F. Hoenicke, Dirk Gara, Alan IBM Thomas J. Watson Research Center Yorktown Heights NY 10598-0218 University of São Paulo LARC - Network and Computer Architecture Laboratory São Paulo SP 05508-900 Brazil

ISBN: (纸本)076952446X

Scientific applications exhibit good spatial and temporal data memory access locality. It is possible to hide memory latency for the Level 3 cache, and reduce contention between multiple cores sharing a single Level 3 cache, by using a prefetch cache to identify data streams which can be profitably prefetched, and decouple the cache line size mismatch between L3 cache and the Level 1 data cache. In this work, a design space exploration is presented, which helped shape the design of the BlueGene/L supercomputer memory sub-system. The prefetch cache consists of a small number of 128 line buffers that speculatively prefetches data from the L3 cache, since applications present some sequential access pattern, this prefetching scheme increases the likelyhood that a request from the Level I data cache will be present in the prefetch cache. Since most compute intensive applications contain a small number of data streams, it is sufficient for the prefetch cache to have small number of line buffers to track and detect the data streams. This paper focuses on the evaluation of stream detection mechanismis and the influence of varying the replacement policies for stream prefetch caches. © 2005 IEEE.

关键词： Supercomputers

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Rail Transit Event Extraction based on the Fusion of Semantic and Local Dependency Features 15

Rail Transit Event Extraction based on the Fusion of Semanti...

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15th IEEE International Conference on Knowledge Graph, ICKG 2024

作者： Chen, Qiang Meng, Haining Bao, Yihao Yang, Mingsong Tong, Xinyu Zhao, Qin Khan, Muhammad Bilal Hei, Xinhong Xi'an University of Technology School of Computer Science and Engineering Xi'an China Xi'an University of Technology School of Computer Science and Engineering Shaanxi Key Laboratory of Network Computing and Security Technology Xi'an China Xi'an University of Technology School of Civil Engineering and Architecture Xi'an China

ISBN: (纸本)9798331508821

Event extraction in rail transit plays a vital role in all stages of design, construction, and final acceptance. Event extraction is a key part of building event logic graph (ELG). However, the difficulty in obtaining semantic features and event local dependencies poses a challenge to accurate event extraction, which hinders the informatization and intelligent development of rail transit projects. To address these challenges, we proposes an event extraction method that fuses semantic and local dependency features. The study initially preprocesses the rail transit design codes dataset and performs sequence labeling. Then, the event trigger words are mined by combining the term frequency-inverse document frequency (TF-IDF) and minimum edit distance (MED) algorithms. Based on the semantic similarity measurement method and the trigger word mining results, the features representation of event semantic information is enhanced by using the Bidirectional Encoder Representations from Transformers (BERT) model and Bi-directional Long Short-Term Memory (BiLSTM) model. At the same time, event arguments are mined and a local dependency graph is generated based on their mining results, and then the enhanced local dependency features are obtained by using the graph convolutional network (GCN). Finally, the event semantic features and local dependency features are fused, and the conditional random field (CRF) is used to predict the labels to obtain the event extraction results. Through the comparison with five baseline methods on the datasets of rail transit design codes, it is found that the Precision, Recall, and F1 score of the proposed method are improved, with an average improvement of 9.604% on Precision, 9.342% on Recall, and 9.730% on F1 score, respectively. The contribution of the sub-modules to the overall performance is further evaluated through ablation experiments, which confirms the effectiveness and feasibility of the proposed method. © 2024 IEEE.

关键词： Semantics

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4-6 Solving a Discrete Logarithm Problem via function field sieve (FFS)

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Journal of the National Institute of Information and Communications Technology 2011年第3-4期58卷 209-217页

作者： Shinohara, Naoyuki Wang, Lihua Matsuo, Shin'ichiro Security Fundamentals Laboratory Network Security Research Institute Computer Algebra Japan Security Fundamentals Laboratory Network Security Research Institute Cryptographic Theory Information Security Japan Security Architecture Laboratory Network Security Research Institute Cryptographic Protocol Japan

Pairings is used to construct many cryptographic systems for which no other efficient implementation is known, such as identity based encryption. Especially, the ηT-paring on supersingular curves over a finite field GF(3n) is efficiently implementable. The security of cryptosystems using such ηT-parings is based on the difficulty to solve Discrete Logarithm Problem (DLP) in GF(3n). Therefore, in the collaborative research of National Institute of Information and Communications Technology (NICT) and Future University-Hakodate, we successfully set a new record for solving the DLP in GF(36.71) of 676-bit size. In this paper, we remark about the collaborative research.

关键词： Cryptography

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Optimal network processor topologies for efficient packet processing

Optimal network processor topologies for efficient packet pr...

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IEEE Conference and Exhibition on Global Telecommunications (GLOBECOM)

作者： Jingnan Yao Yan Luo L. Bhuyan R. Iyer Department of Computer Science and Engineering University of California Riverside USA Network Architecture Laboratory Intel Corporation USA

In this paper, we propose a novel strategy to determine the optimal network processor (NP) topology for the target application tasks. We partition network applications into different stages with the consideration of limited instruction memory of the processing elements (PEs). We develop a theoretical approach to determine an optimal topology of the PEs via multiple pipelines. The idea of multiple pipelining is to exploit the task/packet level parallelism and the pipelines are further optimized to achieve the maximum throughput and resource utilization. Simulation results verify our analytical model and demonstrate the robustness of our approach in different NP configurations.

关键词： network topology Throughput Pipeline processing Switches computer architecture Application software Parallel processing Analytical models Scheduling algorithm Memory management

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Improved recommendation system using friend relationship in SNS 19th

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19th International Conference on Transactions on Computational Collective Intelligence, TCCI 2015

作者： Liao, Qing Wang, Bin Ling, Yanxiang Zhao, Jingling Qiu, Xinyue School of Information and Communication Engineering Beijing University of Posts and Telecommunications Beijing100876 China School of Computer Science Beijing University of Posts and Telecommunications Beijing100876 China Beijing Key Laboratory of Network System Architecture and Convergence Beijing100876 China

ISBN: (纸本)9783662490167

With the rapid development of the Internet, SNS services and 3G commercial mobile applications there have been tremendous opportunities although the development of SNS is very short in China, and the social web game is in the early stage of development. Because of massive users, the potential commercial value of Chinese SNS is still a great mining space. However, a relatively large defects is the precipitation and accumulation on content. The dynamic of friends will affect our own decisions largely, it is favorable for the activity of SNS to increase the number of friends. We have improved the existing models, and conduct experiments to validate it and compare it with previous methods. © Springer-Verlag Berlin Heidelberg 2015.

关键词： Social networking (online)

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Design of Tri-band Unidirectional Printed Antenna 4

Design of Tri-band Unidirectional Printed Antenna

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4th IEEE International Conference on Electronic Information and Communication Technology, ICEICT 2021

作者： Zha, Wende Feng, Botao Chung, Kwok L. Deng, Li College of Electronics and Information Engineering Shenzhen University Shenzhen518060 China School of Computer Science and Engineering Huizhou University Huizhou516007 China Beijing Key Laboratory of Network System Architecture and Convergence Beijing University of Posts and Telecommunications Beijing100876 China

ISBN: (纸本)9781665432030

In this paper, a tri-band unidirectional printed antenna is presented. By employing a torch-shaped structure to cooperate with a pair of side-by-side rectangular patches, triple band characteristics are realized. Simulation results show that the working frequency bands are 806-960 MHz, 1.71-2.7 GHz and 3.3-3.7 GHz, respectively, which cover the LTE700/ GSM850/ GSM900, S-band and WLAN frequency bands. A compact and simple structure with good radiation characteristics is achieved by the proposed antenna, which is suitable for multi-frequency wireless communications. ©2021 IEEE

关键词： Microstrip antennas

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