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International Conference on High Performance Computing

作者： Elkin Garcia Daniel Orozco Rishi Khan Ioannis E. Venetisz Kelly Livingston Guang R. Gao Computer Architecture and Parallel System Laboratory (CAPSL) University of Delaware Newark DE U.S.A ET International Newark DE U.S.A University of Patras Patras GR

Optimization of parallel applications under new many-core architectures is challenging even for regular applications. Successful strategies inherited from previous generations of parallel or serial architectures just return incremental gains in performance and further optimization and tuning are required. We argue that conservative static optimizations are not the best fit for modern many-core architectures. The limited advantages of static techniques come from the new scenarios present in many-cores: Plenty of thread units sharing several resources under different coordination mechanisms. We point out that scheduling and data movement across the memory hierarchy are extremely important in the performance of applications. In particular, we found that scheduling of data movement operations significantly impact performance. To overcome those difficulties, we took advantage of the fine-grain synchronization primitives of many-cores to define percolation operations in order to schedule data movement properly. In addition, we have fused percolation operations with dynamic scheduling into a dynamic percolation approach. We used Dense Matrix Multiplication on a modern manycore to illustrate how our proposed techniques are able to increase the performance under these new environments. In our study on the IBM Cyclops-64, we raised the performance from 44 GFLOPS (out of 80 GFLOPS possible) to 70.0 GFLOPS (operands in on-chip memory) and 65.6 GFLOPS (operands in off-chip memory). The success of our approach also resulted in excellent power efficiency: 1.09 GFLOPS/Watt and 993 MFLOPS/Watt when the input data resided in on-chip and off-chip memory respectively.

关键词： Tiles system-on-chip computer architecture Optimization Program processors Registers Random access memory

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Graph-coloring based resource allocation scheme in relay enhanced cellular system

Graph-coloring based resource allocation scheme in relay enh...

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International Symposium on Wireless Personal Multimedia Communications (WPMC)

作者： Jinlong Cao Tiankui Zhang Zhimin Zeng Dantong Liu Beijing Key Laboratory of Network System Architecture and Convergence Beijing University of Posts and Telecommunications Beijing China School of Electronic Engineering and Computer Science Queen Mary University of London London UK

ISBN: (纸本)9781479904631;9781479904631

Graph-coloring based spectrum resource allocation scheme for relay enhanced cellular (REC) system is proposed in this paper. During the signal transmission process, each subframe is split into two equal time slots (TSs). In TS1, spectrum resource allocation between base station to relay node (BS-RN) link and base station to user equipment (BS-UE) link is studied, while spectrum resources in TS2 are allocated to BS-UE link and RN-UE link. In TS1, traffic load based resource allocation scheme is applied, where the number of resources allocated to BS-RN link is according to the number of one-hop users and two-hop users. In TS2, co-channel interference is considered in the resource allocation process, which can mitigate strong interference between BS and UE, so as to achieve a higher data rate compared with conventional proportional fair (PF) resource allocation scheme. Simulation results show that the proposed scheme can obtain high average throughput as well as user fairness.

关键词： Convergence

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Interference-aware relay selection scheme in cooperative relay networks

Interference-aware relay selection scheme in cooperative rel...

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International Symposium on Wireless Personal Multimedia Communications (WPMC)

ISBN: (纸本)9781479904631;9781479904631

Relay selection scheme with multiple source-destination pairs and multiple potential relays in cooperative relay networks considering co-channel interference (CCI) is proposed in this paper. In cooperative relay networks, which relay nodes are selected has great impact on the system performance. It is an optimization problem for selecting suitable relay nodes. The exhaustive search can solve this problem but the complexity will increase factorially with the network size, i.e., the number of source-destination pairs and the number of relays in the network. This paper proposes a novel quantum particle swarm optimization (QPSO) based relay selection scheme which can maximize the system throughput of the cooperative relay networks but has less computational complexity. Simulation results show that QPSO based relay selection scheme has the ability to search global optimal solution compared with other relay selection schemes in the literature.

关键词： Convergence Complexity theory

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Interference-aware multi-user relay selection scheme in cooperative relay networks

Interference-aware multi-user relay selection scheme in coop...

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IEEE Globecom Workshops

In cooperative relay networks with multiple users and multiple potential relays, which relay nodes are selected has great impact on the system performance. It is an optimization problem for selecting suitable relay nodes. The exhaustive search can solve this problem but the complexity will increase factorially with the network size, i.e., the number of users and the number of relays in the network. In this paper, we formulate both single-objective and multi-objective relay selection problems. For single-objective relay selection problem, only system throughput or fairness is considered. A novel quantum particle swarm optimization (QPSO) based relay selection scheme is proposed. For multi-objective relay selection problem, two contradictive objectives, i.e., system throughput and fairness are considered simultaneously. A novel non-dominated sorting quantum particle swarm optimization (NSQPSO) based relay selection scheme is proposed. Simulation results show that the proposed relay selection schemes have the ability to search global optimal solution but have less computational complexity compared with exhaustive search.

关键词： Tin Optimization Interference Signal to noise ratio Sociology

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A HW/SW co-design of execution migration for shared-ISA heterogeneous chip multiprocessors

A HW/SW co-design of execution migration for shared-ISA hete...

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2013 IEEE 8th International Conference on Networking, architecture and Storage, NAS 2013

作者： Liu, Hongwei Sang, Bo Huang, Jing Qiu, Ji Gao, Xiang Key Laboratory of Computer System and Architecture Chinese Academy of Sciences No. 6 Kexueyuan South Road Zhongguanchun Haidian District Beijing China Institute of Computing Technology Chinese Academy of Sciences No. 6 Kexueyuan South Road Zhongguanchun Haidian District Beijing China Yuquan Road Shijingshan District Beijing China Loongson Corporation No. 10 Kexueyuan South Road Zhongguanchun Haidian District Beijing China Deptartment of Computer Science Purdue University Lawson Computer Science Build 305 N University Street West Lafayette IN United States

ISBN: (纸本)9780769550343

Heterogeneous multi-core processors have strong potential for performance improvement, energy efficiency and area efficiency, compared to the homogeneous multi-core processors. The present methods of execution migration for heterogeneous multi-core processor suffer in efficiency, cost, compatibility, or programmability. In this paper, we propose a HW/SW code sign migration method based on binary-instrumentation. Our method takes full advantage of the shared-ISA. It enhances the performance of heterogeneous chip multiprocessor with low HW/SW cost. And it's not required to modify source codes or compile system. The experiment results show that the efficiency of our method is 3.29 times of kernel simulation. © 2013 IEEE.

关键词： Energy efficiency

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A Dependability Model for TMR system

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International Journal of Automation and computing 2012年第3期9卷 315-324页

作者： Peng, Jun-Jie Liu, Yan-Ping Chen, Yuan-Yuan School of Computer Engineering and Science Shanghai University Shanghai 200072 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

Much research has been done on the dependability evaluation of computer systems. However, much of this is gone no further than study of the fault coverage of such systems, with little focus on the relationship between fault coverage and overall system dependability. In this paper, a Markovian dependability model for triple-modular-redundancy (TMR) system is presented. Having fully considered the effects of fault coverage, working time, and constant failure rate of single module on the dependability of the target TMR system, the model is built based on the stepwise degradation strategy. Through the model, the relationship between the fault coverage and the dependability of the system is determined. What is more, the dependability of the system can be dynamically and precisely predicted at any given time with the fault coverage set. This will be of much benefit for the dependability evaluation and improvement, and be helpful for the system design and maintenance.

关键词： Dependability Markovian model coverage triple-modular-redundancy (TMR) failure rate.

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BTMD: A framework of binary translation based malcode detector

BTMD: A framework of binary translation based malcode detect...

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4th International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, CyberC 2012

作者： Shan, Zheng Guo, Haoran Pang, Jianmin Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China National Digital Switching System Engineering and Technology Research Center Zhengzhou China

ISBN: (纸本)9780769548104

Binary Translation technology is used to convert binary code of one Instruction Set architecture (ISA) into another. This technology can solve the software-inheritance problem and ISA-compatibility between different computers architecture. In this paper, we describe BTMD (Binary Translation based Malcode Detector), a novel framework that exploits static and dynamic binary translation features to detect broad spectrum malware and prevent its execution. By operating directly on binary code with MD Rules on the availability of source code, BTMD is appropriate for translating low-level binary code to high-level proper representation, obtaining CFG (Control Flow Graph) and other high-level Control Structure by MD Parser. Then Critical API Graph based on CFG is generated to do sub graph matching with the defined Malware Behavior Template. MD Engine in BTMD is called to undertake the process to take on the remaining code analysis. Compared with other detection approaches, BTMD is found to be very efficient in terms of detection capability and false alarm rate. © 2012 IEEE.

关键词： Binary codes

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Extendable pattern-oriented optimization directives

Extendable pattern-oriented optimization directives

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作者： Cui, Huimin Xue, Jingling Wang, Lei Yang, Yang Feng, Xiaobing Fan, Dongrui Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Beijing China School of Computer Science and Engineering University of New South Wales Sydney NSW Australia

Algorithm-specific, that is, semantic-specific optimizations have been observed to bring significant performance gains, especially for a diverse set of multi/many-core architectures. However, current programming models and compiler technologies for the state-of-the-art architectures do not exploit well these performance opportunities. In this article, we propose a pattern-making methodology that enables algorithm-specific optimizations to be encapsulated into "optimization patterns". Such optimization patterns are expressed in terms of preprocessor directives so that simple annotations can result in significant performance improvements. To validate this new methodology, a framework, named EPOD, is developed to map these directives into the underlying optimization schemes for a particular architecture. It is difficult to create an exact performance model to determine an optimal or near-optimal optimization scheme (including which optimizations to apply and in which order) for a specific application, due to the complexity of applications and architectures. However, it is trackable to build individual optimization components and let compiler developers synthesize an optimization scheme from these components. Therefore, our EPOD framework provides an Optimization Programming Interface (OPI) for compiler developers to define new optimization schemes. Thus, new patterns can be integrated into EPOD in a flexible manner. We have identified and implemented a number of optimization patterns for three representative computer platforms. Our experimental results show that a pattern-guided compiler can outperform the state-of-theart compilers and even achieve performance as competitive as hand-tuned code. Therefore, such a patternmaking methodology represents an encouraging direction for domain experts' experience and knowledge to be integrated into general-purpose compilers. © 2012 ACM.

关键词： Semantics

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A testability-aware low power architecture

A testability-aware low power architecture

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25th IEEE International system-on-Chip Conference, SOCC 2012

作者： Wang, Gang Wang, Jian Qi, Zi-Chu Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100190 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Loongson Technology Corporation Limited Beijing 100190 China

ISBN: (纸本)9781467312950

Test power consumption is becoming a major concern in low power integrated circuits(ICs). This paper presents a revised low power compression architecture for scan test. In this paper, the variance in power consumption is used to select test pattern during scan test, and a low power feedback MUX is added to the scan chains. Simulation results by mathematical methods show that the proposed test architecture is promising in reduction of power consumption. © 2012 IEEE.

关键词： Electric power utilization

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Cache locking for network processing acceleration

Cache locking for network processing acceleration

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2012 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2012

作者： Su, Wen Gao, Xiang Wang, Jing You, Ruibang Key Laboratory of Computer System and Architecture Chinese Academy of Sciences China Institute of Computing Technology Chinese Academy of Sciences China Graduate University Chinese Academy of Sciences China Loongson Technology Corporation Limited China

ISBN: (纸本)9780769547015

With the dramatic increase in network speed during the past ten years, network processing efficiency has been significantly decreased. In this paper, we propose a network accelerating scheme, which employs cache locking method to reduce data and instruction accessing latency. Interrupts handling and buffer maintenance overheads are obviously decreased. Experimental results show that our solution increases about 22% network bandwidth and reduces 10% latency. © 2012 IEEE.

关键词： Locks (fasteners)

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