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IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Elkin Garcia Daniel Orozco Robert Pavel Guang R. Gao Computer Architecture and Parallel System Laboratory (CAPSL) Electrical and Computer Engineering Department University of Delaware Newark DE USA

ISBN: (纸本)9781467309745

The recent evolution of many-core architectures has resulted in chips where the number of processor elements (PEs) are in the hundreds and continue to increase every day. In addition, many-core processors are more and more frequently characterized by the diversity of their resources and the way the sharing of those resources is arbitrated. On such machines, task scheduling is of paramount importance to orchestrate a satisfactory distribution of tasks with an efficient utilization of resources, especially when fine-grain parallelism is desired or required. In the past, the primary focus of scheduling techniques has been on achieving load balancing and reducing overhead with the aim to increase total performance. This focus has resulted in a scheduling paradigm where Static Scheduling (SS) is preferred to Dynamic Scheduling (DS) for highly regular and embarrassingly parallel applications running on homogeneous architectures. We have revisited the task scheduling problem for these types of applications under the scenario imposed by many-core architectures to investigate whether or not there exists scenarios where DS is better than SS. Our main contribution is the idea that, for highly regular and embarrassingly parallel applications, DS is preferable to SS in some situations commonly found in many-core architectures. We present experimental evidence that shows how the performance of SS is degraded by the new environment on many-core chips. We analyze three reasons that contribute to the superiority of DS over SS on many-core architectures under the situations described: 1) A uniform mapping of work to processors without considering the granularity of tasks is not necessarily scalable under limited amounts of work. 2) The presence of shared resources (i.e. the crossbar switch) produces unexpected and stochastic variations on the duration of tasks that SS is unable to manage properly. 3) Hardware features, such as in-memory atomic operations, greatly contribute to decrea

关键词： Tiles computer architecture Dynamic scheduling Random access memory Throughput Hardware Instruction sets

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MCC: A Load Balancing and Deadlock Free Interconnect Network for Cache Coherent Chip Multiprocessors

MCC: A Load Balancing and Deadlock Free Interconnect Network...

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IEEE International Conference on Computational Science and Engineering, CSE

作者： Liwei Chen Guangfei Zhang Huandong Wang Wenxiang Wang Ling Li Hua Jing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

As the number of cores in chip multiprocessors (CMPs) increases, network-on-chip (NoC) has become a major role in ensuring performance and power scalability. In this paper, we propose multiple-combinational-channel (MCC), a load balancing and deadlock free interconnect network for cache-coherent non-uniform memory accessing (CC-NUMA). In order to make load more balancing and reduce power dissipation, we combine low usage channels and make high usage channels independent and wide enough, since messages transmitted over NoC have different widths and injection rates. Furthermore, based on the in-depth analysis of network traffic, we summarize four traffic patterns and establish several rules to avoid protocol-level deadlock. We implement MCC on a 16-core CMPs, and evaluate the power and performance using universal workloads. The experimental results show that MCC reduces nearly 21% power than multiple-physical-channel with similar throughput. Moreover, MCC improves 10% performance with similar area and power, compared to packet-switching architecture with virtual channels.

关键词： system recovery system-on-a-chip Program processors Bandwidth Load management Throughput Scalability

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A testability-aware low power architecture

A testability-aware low power architecture

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IEEE International SOC Conference

作者： Gang Wang Jian Wang Zi-Chu Qi Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

Test power consumption is becoming a major concern in low power integrated circuits (ICs). This paper presents a revised low power compression architecture for scan test. In this paper, the variance in power consumption is used to select test pattern during scan test, and a low power feedback MUX is added to the scan chains. Simulation results by mathematical methods show that the proposed test architecture is promising in reduction of power consumption.

关键词： Power demand computer architecture Switches Clocks Vectors Switching circuits Compaction

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The EGI software vulnerability group and EMI 2

The EGI software vulnerability group and EMI

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2012 EGI Community Forum / EMI 2nd Technical Conference, EGICF-EMITC 2012

作者： Cornwall, L.A. Heymann, E. STFC Rutherford Appleton Laboratory Harwell Oxford DidcotOX11 OQX United Kingdom Universitat Autonoma de Barcelona Computer Architecture and Operating System Department Campus de Bellaterra Bellaterra Barcelona08193 Spain

This provides an overview of the activities of the European Grid Infrastructure (EGI) Software Vulnerability Group (SVG) and progress made in addressing vulnerabilities in collaboration with the European Middleware Initiative (EMI). This includes a summary of the formally agreed process for handling Software Vulnerabilities reported to the EGI SVG. It also describes the pro-active searching for vulnerabilities via ‘Vulnerability Assessment’ of software packages. Steps taken to prevent new vulnerabilities entering the infrastructure are described. The emphasis is on Grid Middleware as vulnerabilities in this software are generally not handled elsewhere. The collaboration with the Grid middleware software providers, in particular EMI, is described. © Copyright owned by the author(s) under the terms of the Creative Commons Attribution-NonCommercial-ShareAlike Licence.

关键词： Middleware

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A novel HW/SW partitioning with SIMD instructions for AVS video decoder

A novel HW/SW partitioning with SIMD instructions for AVS vi...

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2012 IEEE 7th International Conference on Networking, architecture and Storage, NAS 2012

作者： Chen, Liwei Cong, Ming Huang, Jing Li, Ling Liu, Hongwei Qian, Cheng Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China Chinese Academy of Sciences Graduate University Beijing China Loongson Technology Corporation Limited Beijing China

ISBN: (纸本)9780769547220

In this paper, we propose a novel HW/SW partitioning with SIMD instructions for the real-time AVS video decoder. As the SIMD instructions instead of hardware are used to optimize video decoding, our approach achieves an optimal balance between performance and programmability. We implement the proposed HW/SW partitioning on a 32-bit RISC processor with 256-bit vector extension, and evaluate the performance using some standard high-quality streams of AVS. Results show that the video decoding system can support the real-time decoding of AVS HD video streams. © 2012 IEEE.

关键词： Decoding

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BTMD: A Framework of Binary Translation Based Malcode Detector

BTMD: A Framework of Binary Translation Based Malcode Detect...

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International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, CyberC

作者： Zheng Shan Haoran Guo Jianmin Pang Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China National Digital Switching System Engineering & Technology Research Center Zhengzhou China

Binary Translation technology is used to convert binary code of one Instruction Set architecture (ISA) into another. This technology can solve the software-inheritance problem and ISA-compatibility between different computers architecture. In this paper, we describe BTMD (Binary Translation based Malcode Detector), a novel framework that exploits static and dynamic binary translation features to detect broad spectrum malware and prevent its execution. By operating directly on binary code with MD Rules on the availability of source code, BTMD is appropriate for translating low-level binary code to high-level proper representation, obtaining CFG (Control Flow Graph) and other high-level Control Structure by MD Parser. Then Critical API Graph based on CFG is generated to do sub graph matching with the defined Malware Behavior Template. MD Engine in BTMD is called to undertake the process to take on the remaining code analysis. Compared with other detection approaches, BTMD is found to be very efficient in terms of detection capability and false alarm rate.

关键词： Binary codes Engines computers Decoding Detectors computer architecture Malware

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High efficient memory race recording scheme for parallel program deterministic replay under multi-core architecture

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2012年第1期49卷 64-75页

作者： Liu, Lei Huang, He Tang, Zhimin Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100049 China MIPS Technologies Shanghai 210021 China

Current shared memory multi-core and multiprocessor systems are nondeterministic. When these systems execute a multithreaded application, even if supplied with the same input, they could produce a different output each time. It frustrates debugging and limits the ability to properly test multithreaded code, and is becoming a major stumbling block to the much-needed widespread adoption of parallel programming. The support for deterministic replay of multithreaded execution is greatly helpful in finding concurrency bugs. A memory race recording scheme, named Rainbow, is proposed. Its core idea is to make inter-thread communications fully deterministic. The unique feature of Rainbow is that it precisely sets up happens-before relationships between conflicting memory operations among different threads. By using effective, bloom-filter based, coherence history queue, Rainbow removes redundant happens-before relations implied in the already generated log and enables a compact log. Rainbow adds the modest hardware to the base multi-core processors, and the coherence protocol is unmodified. The analysis results show that Rainbow reduces the log size by 17% of a state-of-the-art scheme, and the records execution speed is similar to that of release consistency (RC) execution and replays at about 93% of its speed. The determinism can be provided with little performance cost using our architecture proposals on the state-of-the-art hardware, and the software-only approaches can be utilized on existing systems without problem.

关键词： Parallel programming

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A CROSS-PLATFORM CONTEXT-AWARE APPLICATION DEVELOPING FRAMEWORK FOR MOBILE TERMINALS

A CROSS-PLATFORM CONTEXT-AWARE APPLICATION DEVELOPING FRAMEW...

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2012 IEEE 2nd International Conference on Cloud Computing and Intelligence systems

作者： Pingyi Wang Jingling Zhao Qing Liao School of Computer Science Beijing University of Posts and Telecommunications Beijing Key Laboratory of Network System Architecture and Convergence Beijing University of Posts and Telecommunications

The increasing number of mobile terminals facilitates the development of context-aware applications. However, developing a context aware application is still a complex work, which involves mechanisms of context acquisition and context processing. In order to release the developer’s burden, many context aware frameworks emerged. But none of them yet has sufficient consideration of mobile environment characteristics. Besides, restricted to the mobile platform, the developed application could not achieve cross-platform deployment. A cross-platform context-aware application developing framework for mobile terminals is proposed in this paper. This framework could shield system differences, centralize context acquisition, context modeling, context storing, context interpretation and context aggregation for many context aware applications on the same terminal. Applying the framework, data of same sensor would not be duplicated processed by many context aware applications. Context aware application would be built faster. And mobile terminal resources would be used more efficiently.

关键词： Context-awareness Cross-platform Mobile terminal Framework

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A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems 12

A clustering-based scheme for concurrent trace in debugging ...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Jianliang Gao Jianxin Wang Yinhe Han Lei Zhang Xiaowei Li School of Information Science and Engineering Central South University China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9783981080186

Concurrent trace is an emerging challenge when debugging multicore systems. In concurrent trace, trace buffer becomes a bottleneck since all trace sources try to access it simultaneously. In addition, the on-chip interconnection fabric is extremely high hardware cost for the distributed trace signals. In this paper, we propose a clustering-based scheme which implements concurrent trace for debugging Network-on-Chip (NoC) based multicore systems. In the proposed scheme, a unified communication framework eliminates the requirement for interconnection fabric which is only used during debugging. With clustering scheme, multiple concurrent trace sources can access distributed trace buffer via NoC under bandwidth constraint. We evaluate the proposed scheme using Booksim and the results show the effectiveness of the proposed scheme.

关键词： Multicore processing Bandwidth Fabrics Debugging Clustering algorithms Real time systems system-on-a-chip

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New Methodologies for Parallel architecture

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Journal of computer Science & Technology 2011年第4期26卷 578-587页

作者：范东睿李晓维李国杰 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences

Moore＇s law continues to grant computer architects ever more transistors in the foreseeable future, and parallelism is the key to continued performance scaling in modern microprocessors. In this paper, the achievements in our research project, which is supported by the National Basic Research 973 Program of China, on parallel architecture, are systematically presented. The innovative approaches and techniques to solve the significant problems in parallel architecture design are smnmarized, including architecture level optimization, compiler and language-supported technologies, reliability, power-performance efficient design, test and verification challenges, and platform building. Two prototype chips, a multi-heavy-core Godson-3 and a many-light-core Godson-T, are described to demonstrate the highly scalable and reconfigurable parallel architecture designs. We also present some of our achievements appearing in ISCA, MICRO, ISSCC, HPCA, PLDI, PACT, IJCAI, Hot Chips, DATE, IEEE Trans. VLSI, IEEE Micro, IEEE Trans. computers, etc.

关键词： architecture multi-core many-core parallelism

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