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Wear rate leveling: Lifetime enhancement of PRAM with endurance variation

Wear rate leveling: Lifetime enhancement of PRAM with endura...

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作者： Dong, Jianbo Zhang, Lei Han, Yinhe Wang, Ying Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781450306362

The limited write endurance of phase change random access memory (PRAM) is one of the major obstacles for PRAM-based main memory. Wear leveling techniques were proposed to extend its lifetime by balancing writes traffic. Another important concern that need to be considered is endurance variation in PRAM chips. When different PRAM cells have distinct endurance, balanced writes will result in lifetime degradation due to the weakest cells. Instead of balancing writes traffic, in this paper we propose wear rate leveling (WRL), a variant of wear leveling, to balance wear rates (i.e., writes traffic/edudrance) of cells across the PRAM chip. After investigating writing behavior of applications and endurance variation, we propose an architecture-level WRL mechanism. Moreover, there is an important tradeoff between endurance improvement and swapping data volume. To co-optimize endurance and swapping, a novel algorithm, Max Hyper-weight Rematching, is proposed to maximize PRAM lifetime and minimize performance degradation. Experimental results show 19x endurance improvement to prior Wear Leveling © 2011 ACM.

关键词： Phase change memory

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Flex memory: Exploiting and managing abundant off-chip optical bandwidth

Flex memory: Exploiting and managing abundant off-chip optic...

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作者： Wang, Ying Zhang, Lei Han, Yinhe Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9783981080179

The emerging nanophotonic technology can avoid the limitation of I/O pin count, and provide abundant memory bandwidth. However, current DRAM organization has mainly been optimized for a higher storage capacity and package pin utilization. The resulted data fetching mechanism is quite inefficient in performance and energy saving, and cannot effectively utilize the abundant optical bandwidth in off-chip communication. This paper inspects the opportunity brought by optical communication, and revisits the DRAM memory architecture considering the technology trend towards multiprocessors. In our FlexMemory design, super-line prefetching is proposed to boost system performance and promote energy efficiency, which leverages the abundant photonic bandwidth to enlarge the effective data fetch size per memory cycle. To further preserve locality and maintain service parallelism for different workloads, page folding technique is employed to achieve adaptive data mapping in photonics-connected DRAM chips via optical wavelengths allocation. By combining both techniques, surplus off-chip bandwidth can be utilized and effectively managed adapting to the workloads intensity. Experimental results show that our FlexMemory achieves considerable improvements in performance and energy efficiency. © 2011 EDAA.

关键词： Dynamic random access storage

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High-efficient architecture of Godson-T many-core processor 23

High-efficient architecture of Godson-T many-core processor

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23rd IEEE Hot Chips Symposium, HCS 2011

作者： Fan, Dongrui Zhang, Hao Wang, Da Ye, Xiaochun Song, Fenglong Zhang, Junchao Fan, Lingjun Advanced Micro-System Group National Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

This article consists of a collection of slides from the author's conference presentation on the special features, system design, processing capabilities, and targeted markets for AMS's Godson-T microprocessor...

ISBN: (纸本)9781467388771

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A priority-aware NoC to reduce squashes in Thread Level Speculation for Chip Multiprocessors

A priority-aware NoC to reduce squashes in Thread Level Spec...

引用

9th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2011

作者： Dai, Wenbo An, Hong Li, Qi Li, Gongming Deng, Bobin Wu, Shilei Li, Xiaomei Liu, Yu School of Computer Science and Technology University of Science and Technology of China Hefei China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769544281

Thread Level Speculation (TLS) is a technique aims at boosting the performance of sequential programs running on Chip Multiprocessors (CMPs) by automatically parallelizing them. It exempts programmers from the heavy task of parallel programming. But its performance may suffer from frequent squashing caused by inter-thread data dependency violation. In this paper, we propose a Network-on-Chip (NoC) in CMP that employs a priority-aware packet arbitration policy. Packet scheduling guided by such policy reduces the occurrence of TLS squashes. Simulation results with 5 applications show that our policy reduces squashes by 22% in best case and 15% on average. Moreover, our priority-aware approach could be generalized to similar scenarios in which different threads running on CMP manifest different priorities. © 2011 IEEE.

关键词： Network-on-chip

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A non-blocking programming framework for pipeline application on multi-core platform

A non-blocking programming framework for pipeline applicatio...

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9th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2011

作者： Li, Xiaoqiang An, Hong Liu, Gu Han, Wenting Xu, Mu Zhou, Wei Li, Qi School of Computer Science and Technology University of Science and Technology of China Hefei China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769544281

Many applications meet certain programming patterns like pipeline, fork-join, do-all etc. While tools such as OS threads and OpenMP allow programmers only to express task or data parallelism, special support for programming patterns is distinctly lacking. Intel threading building blocks (TBB) is developed to address this problem, but its scheduler is general and not optimized for any of its parallel algorithms which include pipeline specially. In this paper, we provide a non-blocking framework for pipeline application on multi-core platform. We target linear pipeline in which each filter has one entrance and one exit. We design a novel work-stealing scheduler optimized specially for pipeline application: first, priority based stealing, priority is calculated for each filter in pipeline so that a worker can find the optimal "victim" easily when it needs to steal;second, multiple tasks can be stolen at a time so that much stealing time is reduced. A nonblock queue is used to store intermediate result to reduce lock overhead and increase scalability. We apply our framework to four case studies, including text filter, twofish, ferret, dedup. And our framework reduces execution time of TBB by 72% in best case and 20% on average on an 8 core machine. © 2011 IEEE.

关键词： Pipelines

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CHMasters: A scalable and speed-efficient metadata service in distributed file system

CHMasters: A scalable and speed-efficient metadata service i...

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2011 12th International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2011

作者： Xu, Min Zhou, Junrui Zhou, Wei An, Hong Department of Computer Science and Technology University of Science and Technology Hefei 230026 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100080 China

ISBN: (纸本)9780769545646

Distributed file system (DFS) is playing important roles of supporting large distributed data-intensive applications to meet storage needs. Typically, the design of DFS, such as GFS in Google, DMS in Cisco and TFS in Alibaba, is driven by observations of specific application workloads, internal demands and technological environment. In such systems, the metadata service is a critical factor that can affect the file system performance and availability to a great degree. Five requirements have been summarized for the metadata service: location transparent file service, smart director, efficient speed, strong scalability and friendly collaborator. In this paper, we present metadata service module called CHMasters in our DFS. Consistent hashing protocol is used to relieve potential hot spots on name servers. Files'metadata and master nodes are mapped into the same hash space by consistent hash function. And then files'metadata are scattered to master nodes by clockwise "closest" principle. Chunkserver acts as a client when report its chunks info. Only a small proportion of files'metadata will be rehashed when master nodes state change. A new scalable file mapping strategy is also proposed to map file sizes from few MB to several GB efficiently. After intensive experiments, it shows CHMasters is satisfying the above five requirements. © 2011 IEEE.

关键词： Metadata

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Beyond green: Evolution to adaptability and recyclability

Beyond green: Evolution to adaptability and recyclability

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2011 IEEE/ACM International Conference on Green Computing and Communications, GreenCom 2011

作者： Sun, Yuzhong Song, Ying Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769544663

In current social computing system, not only hardware but also software experiences a directly discarded mode. Such directly discarded mode may result in huge waste. The major challenge in green computing is the recyclability of the computing system. In order to address this challenge in the software field, this paper proposes a design idea of green software embodying the adaptability and recyclability. The adaptable and recyclable strategy may consist of two phases. The first one is compressing the increasingly deeper software stack;another one is keeping the functionality recycling and code reuse. The adaptability and recyclability mean automatically decomposing the complex software into several parts which are ease to be reused and automatically selecting the feasible parts for the on-writing software. And we also explore the system software design path to adaptability and recyclability in our previous work as well as in the future. © 2011 IEEE.

关键词： Software design

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Software and hardware co-designed multi-level TLBs for chip multiprocessors

Software and hardware co-designed multi-level TLBs for chip ...

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11th IEEE International Conference on computer and Information Technology, CIT 2011 and 11th IEEE International Conference on Scalable Computing and Communications, SCALCOM 2011

作者： Zhang, Xiaohui Cong, Ming Chen, Guangqiang Key Laboratory of Computer System and Architecture Institute of Computing Technology Graduate University Beijing China National University of Defense Technology Changsha China

ISBN: (纸本)9780769543888

Translation Lookaside Buffers ( TLBs ) have a significant impact on system performance. Numerous prior studies focus on TLBs design for uniprocessors. With the advent of chip multiprocessors (CMPs), we need a shift to TLBs for chip multiprocessors. This paper presents a software-implemented level-two TLB-SL2-TLB which is a shared level-two TLB for multiprocessors. It not only reduces the cost of TLB refill handler for every processor core, but also reduces the redundant TLB misses' cost for CMPs effectively. Today, CMPs typically employ private per-core TLBs. SL2-TLB together with the hardware TLBs make up a software-hardware co-designed multilevel TLB system which brings great benefit to system performance while avoiding changing the hardware TLB. So it is a convenient and efficient method for CMPs' TLB performance improvement. The benefit brought by SL2-TLB to SPECCPU2000 is less than that to SPECCPU2006, about 5% and 7% separately. Thereinto, the average performance improvement of SPECint 2006 reaches about 12.7%. That is because the overhead for TLB refill is small when the cache is large enough to avoid a miss as walking the page table of applications with small memory footprints. The further optimization for SL2-TLB is kept the SL2-TLB table stay in L2 cache forever by the cache locking scheme. SL2-TLB together with cache locking scheme improves the performances by over 13% for SPECint 2006. And an average performance improvement of over 7% is brought to the new emerging parallel benchmark suite- Princeton Application Repository for Shared-Memory computers (PARSEC). And all the above evaluations are done on Godson-3 processors which is the latest generation of China's most powerful microprocessor family. © 2011 IEEE.

关键词： Benchmarking

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Parallelizing a machine translation decoder for multicore computer

Parallelizing a machine translation decoder for multicore co...

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2011 7th International Conference on Natural Computation, ICNC 2011

作者： Chen, Long Huo, Wei Mi, Haitao Zhang, Zhaoqing Feng, Xiaobing Li, Zhiyuan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Department of Computer Science Purdue University West Lafayette IN 47907 United States

ISBN: (纸本)9781424499533

Machine translation (MT), with its broad potential use, has gained increased attention from both researchers and software vendors. To generate high quality translations, however, MT decoders can be highly computation intensive. With significant raw computing power, multi-core microprocessors have the potential to speed up MT software on desktop machines. However, retrofitting existing MT decoders is a nontrivial issue. Race conditions and atomicity issues are among those complications making parallelization difficult. In this article, we show that, to parallelize a state-of-the-art MT decoder, it is much easier to overcome such difficulties by using a process-based parallelization method, called functional task parallelism, than using conventional thread-based methods. We achieve a 7.60 times speed up on an 8-core desktop machine while making significantly less changes to the original sequential code than required by using multiple threads. © 2011 IEEE.

关键词： Machine translation

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An efficient and flexible task management for many cores

An efficient and flexible task management for many cores

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作者： Yuan, Nan Yu, Lei Fan, Dong-Rui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100039 China

ISBN: (纸本)9783642245671

This paper presents the design and implementation of a runtime system (named "GodRunner") on Godson-T many-core processor to support task-level parallelism efficiently and flexibly. GodRunner abstracts underlying hardware resource, providing ease-of-use programming interface. A two-grade task management mechanism is proposed to support both coarse-grained and fine-grained multithreading efficiently. Two load-balanced scheduling policies are combined flexibly in GodRunner. The software-controlled task management makes GodRunner more configurable and extensible than hard-wired ones. The experiment shows that the tasking overhead in GodRunner is as small as hundreds of cycles, which is about the hundreds of times faster than the conventional Pthread based multithreading on a SMP machine. Furthermore, our approach scales well and supports fine-grained tasks as small as 20k cycles optimally. © 2011 Springer-Verlag Berlin Heidelberg.

关键词： computer architecture

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