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PartitionSim: A parallel simulator for many-cores

Jisuanji Xuebao/Chinese Journal of computers 2011年第11期34卷 2084-2092页

作者： Jiao, Shuai Xu, Wei-Zhi Tang, Shi-Bin Fan, Dong-Rui Sun, Ning-Hui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acad. of Sci. Beijing 100190 China Graduate University of Chinese Acad. of Sci. Beijing 100049 China

This paper introduces PartitionSim, a parallel simulator for future thousand-core processors with software-managed cache coherence. The purpose of PartitionSim is to improve the simulation performance of many-core architectures at the expense of little accuracy sacrifice. To achieve this goal, we propose a novel technique: timing partition. Timing partition is based on such an observation: in a target system, interacting components communicate with each other and impose simulation synchronization while non-interacting components don't communicate with each other and allow asynchronous simulation. It divides the target timing models into two groups: non-interacting group and interacting group. Non-interacting timing models are simulated by host threads that synchronize little with each other to improve speed and hurt little accuracy, while interacting timing models are simulated by host threads that synchronize strictly with each other to preserve accuracy. Using PartitionSim, We have simulated a target composed of thousands of cores on a 16-core SMP machine. The evaluation results show that PartitionSim scales well with near linear speedup and has considerable performance (up to 25MIPS) at the expense of little accuracy sacrifice (average 0.92%).

关键词： Timing circuits

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JVM virtual method invoking optimization based on CAM table

JVM virtual method invoking optimization based on CAM table

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IEEE International Conference on Networking, architecture and Storage

作者： Cai, Songsong Yang, Yongqiang Lin, Chuanwen Liu, Qi Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China Dept. of Computer Science and Technology University of Science and Technology of China Hefei China Loongson Technology Corporation Limited Beijing China

ISBN: (纸本)9780769545097

In Java programs, it needs to use the information of the method type to resolve the virtual method dynamically, which restricts the performance greatly. Currently, the solution is mainly the technique of inline caching, which can be divided into two categories: monomorphic inline caching and polymorphic inline caching. Because of the simple implementation of monomorphic inline caching, it is more commonly used, but it cannot resolve the problem of frequently seeing different types of objects at one call site. Although polymorphic inline caching can solve this problem, it is costly. This paper presents the CAM hardware table, proposes a virtual method invoking mechanism based on software and hardware co-design. It solves the problem of frequently seeing different types of objects at one call site, and does not introduce additional overhead. The experimental evaluation shows that it improves the cached hit rate from 13.3% to 76.4% and improves 16.2% performance of the virtual test;it improves the performance of SPECjvm98 by 6.4% on average. © 2011 IEEE.

关键词： Virtual reality

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PADS: A Pattern-Driven Stencil Compiler-Based Tool for Reuse of Optimizations on GPGPUs

PADS: A Pattern-Driven Stencil Compiler-Based Tool for Reuse...

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International Conference on Parallel and Distributed systems (ICPADS)

作者： Dongni Han Shixiong Xu Li Chen Lei Huang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Computer Science Department Prairie View A&M University USA

Stencil computations are core of wide range of scientific and engineering applications. A lot of efforts have been put into improving efficiency of stencil calculations on different platforms, but unfortunately it is not easy to reuse. In this paper we present a PAttern-Driven Stencil compiler-based tool and a simple tuning system to reuse those well optimized methods and codes. We also suggest extensions to OpenMP, depicting high-level data structures in order to facilitate recognition of various stencil computation patterns. The PADS allows programmers to rewrite kernel of stencils or reuse source-to-source translator outputs as optimized stencil template codes with related tuning parameters, In addition, PADS consists of a OpenMP to CUDA translator and code generator using optimized template codes. It also obtains architecture-specific parameters to tune stencils across different GPU platforms. To demonstrate our system flexibility and performance portability, we illustrate four different stencil computations, Laplacian operator with Jacobi iterative method, divergence operator, 3 dimension 25 point stencil and a 2D heat equation using ADI method with periodic boundary conditions. PADS succeeds in generating all these four stencil codes using different optimization strategies and delivers a promising performance improvement.

关键词： Pattern matching Kernel Tuning Libraries Optimization Generators

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Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors

Transparent dynamic binding with fault-tolerant cache cohere...

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International Conference on Dependable systems and Networks (DSN)

作者： Shuchang Shan Yu Hu Xiaowei Li Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level fault-tolerant approaches bind two cores to implement redundant execution and error detection. However, along with more cores integrated into one chip, existing static and dynamic binding schemes suffer from the scalability problem when considering the violation effects caused by external write operations. In this paper, we present a transparent dynamic binding (TDB) mechanism to address the issue. Learning from static binding schemes, we involve the private caches to hold identical data blocks, thus we reduce the global masters-lave consistency maintenance to the scale of the private caches. With our fault-tolerant cache coherence protocol, TDB satisfies the objective of private cache consistency, therefore provides excellent scalability and flexibility. Experimental results show that, for a set of parallel workloads, the overall performance of our TDB scheme is very close to that of baseline fault-tolerant systems, outperforming dynamic core coupling by 9.2%, 10.4%, 18% and 37.1% when considering 4, 8, 16 and 32 cores respectively.

关键词： Master-slave Fault tolerance Fault tolerant systems Coherence system-on-a-chip Pipelines

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Desynchronize a legacy floating-point adder with operand-dependant delay elements

Desynchronize a legacy floating-point adder with operand-dep...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Jun Xu Hong Wang Key Laboratory of Computer System and Architecture ICT Chinese Academy and Sciences Beijing China University of the Chinese Academy of Sciences Beijing Beijing CN

De-synchronization is a fast and simple way to design an asynchronous circuit, but it has inherent limitation on performance improvement due to the traditional delay element implementation method. In this paper, a length-variable delay element is introduced to help us design a high performance asynchronous floating-point adder. The completion time can be automatically adjusted depending on the operation and operand; therefore, the useless waiting time and energy are effectively eliminated. The experimental result shows that our proposal has 33% performance advantages over the synchronous version and the traditional desynchronized implementation.

关键词： Delay Pipelines Adders Asynchronous circuits Synchronization Proposals

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A computer-supported collaborative learning platform based on clouds

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Journal of Computational Information systems 2011年第11期7卷 3811-3818页

作者： Li, Jiandun Peng, Junjie Zhang, Wu Han, Fangfang Yuan, Qin Joint Lab of Cloud Computing School of Computer Engineering and Science Shanghai University Shanghai 200072 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

computer-supported collaborative learning (CSCL) is an emerging branch of learning science concerned with studying how people can learn together with the help of computers. As an indispensable ingredient, computer mediation evolves through couples of phases, e.g. centralized server, peer-to-peer network, grid computing. Nevertheless, with daily rising trend on requirement's dynamic changes in service, existing models fall short to respond on demand. Thus, in this paper, by taking advantage of cloud computing, we propose a feasible CSCL platform and the experiments show that it can not only fulfill the basic requirement of CSCL, but also respond to learner's dynamic need on demand. Copyright © 2011 Binary Information Press.

关键词： Peer to peer networks

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Empirical design bugs prediction for verification

Empirical design bugs prediction for verification

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Design, Automation and Test in Europe Conference and Exhibition

作者： Qi Guo Tianshi Chen Haihua Shen Yunji Chen Yue Wu Weiwu Hu Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Coverage model is the main technique to evaluate the thoroughness of dynamic verification of a Design-under-Verification (DUV). However, rather than achieving a high coverage, the essential purpose of verification is to expose as many bugs as possible. In this paper, we propose a novel verification methodology that leverages the early bug prediction of a DUV to guide and assess related verification process. To be specific, this methodology utilizes predictive models built upon artificial neural networks (ANNs), which is capable of modeling the relationship between the high-level attributes of a design and its associated bug information. To evaluate the performance of constructed predictive model, we conduct experiments on some open source projects. Moreover, we demonstrate the usability and effectiveness of our proposed methodology via elaborating experiences from our industrial practices. Finally, discussions on the application of our methodology are presented.

关键词： computer bugs Predictive models Complexity theory Measurement Training data Training Correlation

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Cross-layer optimized placement and routing for FPGA soft error mitigation

Cross-layer optimized placement and routing for FPGA soft er...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Keheng Huang Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

As the feature size of FPGA shrinks to nanometers, soft errors increasingly become an important concern for SRAM-based FPGAs. Without consideration of the application level impact, existing reliability-oriented placement and routing approaches analyze soft error rate (SER) only at the physical level, consequently completing the design with suboptimal soft error mitigation. Our analysis shows that the statistical variation of the application level factor is significant. Hence in this work, we first propose a cube-based analysis to efficiently and accurately evaluate the application level factor. And then we propose a cross-layer optimized placement and routing algorithm to reduce the SER by incorporating the application level and the physical level factor together. Experimental results show that, the average difference of the application level factor between our cube-based method and Monte Carlo golden simulation is less than 0.01. Moreover, compared with the baseline VPR placement and routing technique, the cross-layer optimized placement and routing algorithm can reduce the SER by 14% with no area and performance overhead.

关键词： Routing Wires Circuit faults Field programmable gate arrays Monte Carlo methods Algorithm design and analysis Accuracy

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GPU-accelerated fault simulation and its new applications

GPU-accelerated fault simulation and its new applications

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International Symposium on VLSI Design, Automation and Test

作者： Huawei Li Dawen Xu Kwang-Ting Cheng Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Department of Electrical and Computer Engineering University of California Santa Barbara CA USA

GPUs have recently been explored as a new general-purpose computing platform, which are suitable for the acceleration of compute-intensive EDA applications. In this paper we describe a GPU-based one- to n-detection fault simulator for both stuck-at and transition faults, which demonstrates a 20X speedup over a commercial CPU-based fault simulator. We further show new fault-simulation-based test selection applications enabled by this accelerated fault simulation. Our results demonstrate that the tests selected from the applications achieve higher fault coverages for 1-to-n detections with steeper fault coverage curves, as well as a better delay test quality, in comparison with tests deterministically generated by commercial ATPG tools.

关键词： Circuit faults Graphics processing unit Instruction sets Delay Integrated circuit modeling Logic gates Computational modeling

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An Efficient Shared Memory Based Virtual Communication system for Embedded SMP Cluster

An Efficient Shared Memory Based Virtual Communication Syste...

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International Conference on Networking, architecture, and Storage (NAS)

作者： Wenxuan Yin Xiang Gao Xiaojing Zhu Deyuan Guo Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Institute of Microelectronics Tsinghua University Beijing China

With the prevalence of multi-core processors, it is a trend that the embedded cluster deploys SMP nodes to gain more computing power. As a crucial issue, the MPI inter-process communication has been suffering the contradiction between high performance and embedded constraints. Moreover, there is a big performance gap between intra- and inter-node communication for different infrastructures. In this paper, we design a virtual communication system called SMVN, which extends the shared memory mechanism typically used in intra-node case into the inter-node case. The SMVN utilizes the HT inter-chip interconnect interface in Godson-3A SMP nodes to build a mesh topology. It is Ethernet compatible by simulating bottom layers of TCP/IP protocol. With the design, the node interconnection can get rid of NICs, cables and switches. Furthermore, we exploit the zero-copy scheme and other optimizations to improve the performance. We port the MPICH2 library by socket channel and formulate its process allocation. The MPI latency and bandwidth tests show that the performance difference between two levels is small. The inter-node bandwidth is 27.3 MB/s, which is more than twice the theoretical peak value of 100 Mb Ethernet and reaches 84% of the intra-node performance.

关键词： Program processors IP networks Protocols computer architecture Bandwidth Resource management Synchronization

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