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Pattern-unit based regular expression matching with reconfigurable function unit

Pattern-unit based regular expression matching with reconfig...

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2010 International Conference on Computational Science and Its Applications, ICCSA 2010

作者： Cong, Ming An, Hong Cao, Lu Liu, Yuan Li, Peng Wang, Tao Yu, Zhi-Hong Liu, Dong School of Computer Science and Technology University of Science and Technology of China Hefei 230027 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100190 China Intel China Research Center Beijing 100190 China

ISBN: (纸本)3642121888

Regular Expression (RE) is widely used in many aspects due to its high expressiveness, flexibility and compactness, which requires a high-performance and efficient matching method. A novel approach to accelerate RE pattern matching based on Pattern-Unit (PUREM) is proposed here, in which Pattern-Unit matching is accomplished by a Reconfigurable Function Unit (RFU). The RFU can be integrated into the pipeline of CPU architecture and shares matching jobs with software, without wrecking the compatibility of applications. Compared with other works, our approach offers a flexible mechanism under which hardware does NOT need to vary with RE patterns, and it holds the scalability that can be easily extended to most RE applications and software. For validation, the PUREM HW/SW system has been implemented on the Snort v2.8 and PCRE v7.6 applications. The experimental results show a significant speedup of 3~4x compared to the software performance on a 2GHz Pentium IV machine, where our RFU logic mapped onto Xilinx Virtex-5 XC5VLX50 only takes up 17% resource. © 2010 Springer-Verlag Berlin Heidelberg.

关键词： Pattern matching

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VMGuard: An integrity monitoring system for management virtual machines

VMGuard: An integrity monitoring system for management virtu...

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16th IEEE International Conference on Parallel and Distributed systems, ICPADS 2010

作者： Fang, Haifeng Zhao, Yiqiang Zang, Hongyong Huang, H. Howie Song, Ying Sun, Yuzhong Liu, Zhiyong Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China George Washington University WA United States

ISBN: (纸本)9780769543079

A cloud computing provider can dynamically allocate virtual machines (VM) based on the needs of the customers, while maintaining the privileged access to the Management Virtual Machine that directly manages the hardware and supports the guest VMs. The customers must trust the cloud providers to protect the confidentiality and integrity of their applications and data. However, as the VMs from different customers are running on the same host, an attack to the management virtual machine will easily lead to the compromise of the guest VMs. Therefore, it is critical for a cloud computing system to ensure the trustworthiness of management VMs. To this end, we propose VMGuard, an integrity monitoring and detecting system for management virtual machines in a distributed environment. VMGuard utilizes a special VM, Guard Domain, which runs on each physical node to monitor the co-resident management VMs. The integrity measurements collected by the Guard Domains are sent to the VMGuard server for safe store and independent analysis. The experimental evaluation of a Xen-based prototype shows that VMGuard can quickly detect the root kit attacks while the performance overhead is low. © 2010 IEEE.

关键词： Virtual machine

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Formula-Oriented Compositional Minimization in Model Checking

Formula-Oriented Compositional Minimization in Model Checkin...

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2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

作者： Bowen Chen Haihua Shen Wenhui Zhang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade State Key Laboratory of Computer Science Institute of Software Chinese Academy of Sciences Beijin

This paper presents a new approach to reduce finite state machines with respect to a CTL formula to alleviate state explosion problem. Reduction is achieved by removing parts useless to the formula of original machines. The main contribution of this paper is to exploit relations among subformulas of the CTL formula so as to gain more reduction, as well as to extend traditional pruning method, which handles only existential formulas, to handle universal formulas. Based on this kind of reduction, verification of a large system, which usually consists of several components, can be done by evaluating properties on a reduced version of the system, which is built by composing components of the system one by one while doing reduction after each composition. Experimental results show the effectiveness of the approach. Especially when a property is written in a more detailed way, that is to describe the system part by part, the approach has a great potential.

关键词： Formula-Oriented Compositional Minimization CTL Model Checking Formal Verification

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DCMTs: Supporting dynamically created migratory threads

DCMTs: Supporting dynamically created migratory threads

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International Conference on Computational Science and Engineering

作者： Zhu, Yueting Zhang, Wu Jiang, Hai Lei, Yu Peng, Junjie Department of Computer Science and Engineering Shanghai University Shanghai China Department of Computer Science Arkansas State University Jonesboro AR United States Department of Computer Science and Engineering University of Texas Arlington TX United States Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9780769543239

Thread migration is an effective technique for fault resilience and load balancing in high performance computing. However, flexible thread migration is not easy to achieve. In this paper, we present an approach to creating migratory threads dynamically at application level. The targets must be executable source files. Compared to the static ones, the number of threads created during migration with the new scheme is independent from the context. Various thread cases are considered for migration. Thread state is handled at application level. Variables are saved in structures in C language for speedy state construction. In order to solve the inability of traditional methods in tracking the created threads, a tree of active function calls is used to record the callback. The preprocessor of the proposed one is written in YACC for accuracy and programmability. The migration enabling process is transparent to programmers with the help of the preprocess. The experimental results have demonstrated the effectiveness of this approach. © 2010 IEEE.

关键词： Fault tolerance

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Building a personal high performance computer with heterogeneous processors

Building a personal high performance computer with heterogen...

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International Conference on Grid and Cloud Computing

作者： Li, Qiang Huo, Zhigang Sun, Ninghui National Research Center for Intelligent Computing Systems Beijing 100190 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing 100190 China

ISBN: (纸本)9780769543130

Personal high performance computer (PHPC) requires lower cost and high performance. The Teraflops PHPC systems with special accelerator units like GPGPU have been presented, but they have difficulties in programming, compatibility and applicability. In this paper, we present HPP-PHPC, a hybrid architecture of heterogeneous processors connected by non-coherent off-chip system bus. The performance of HPP-PHPC is ensured by special processors integrated with vector units and high-efficiency interconnection between heterogeneous processors. And by the adoption of general processors and features like global physical address space and synchronization semantics in hardware, HPP-PHPC is more compatible and convenient for massage passing and PGAS programming model. Also it is more applicable to most applications, including those with many execution branches. Initial results obtained from our prototype system have proved our design. © 2010 IEEE.

关键词： Semantics

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DMA cache: Using on-chip storage to architecturally separate I/O data from CPU data for improving I/O performance

DMA cache: Using on-chip storage to architecturally separate...

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IEEE Symposium on High-Performance computer architecture

作者： Dan Tang Yungang Bao Weiwu Hu Mingyu Chen Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

ISBN: (纸本)9781424456581

As technology advances both in increasing bandwidth and in reducing latency for I/O buses and devices, moving I/O data in/out memory has become critical. In this paper, we have observed the different characteristics of I/O and CPU memory reference behavior, and found the potential benefits of separating I/O data from CPU data. We propose a DMA cache technique to store I/O data in dedicated on-chip storage and present two DMA cache designs. The first design, Decoupled DMA Cache (DDC), adopts additional on-chip storage as the DMA cache to buffer I/O data. The second design, Partition-Based DMA Cache (PBDC), does not require additional on-chip storage, but can dynamically use some ways of the processor's last level cache (LLC) as the DMA cache. We have implemented and evaluated the two DMA cache designs by using an FPGA-based emulation platform and the memory reference traces of real-world applications. Experimental results show that, compared with the existing snooping-cache scheme, DDC can reduce memory access latency (in bus cycles) by 34.8% on average (up to 58.4%), while PBDC can achieve about 80% of DDC's performance improvements despite no additional on-chip storage.

关键词： Cache storage Delay Bandwidth Buffer storage system-on-a-chip Laboratories computer architecture Emulation Throughput Hard disks

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GenerOS: An asymmetric operating system kernel for multi-core systems

GenerOS: An asymmetric operating system kernel for multi-cor...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Qingbo Yuan Jianbo Zhao Mingyu Chen Ninghui Sun Key Laboratory of Computer System and Architecture Institute of Compute Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424464425

Due to complex abstractions implemented over shared data structures protected by locks, conventional symmetric multithreaded operating system kernel such as Linux is hard to achieve high scalability on the emerging multi-core architectures, which integrate more and more cores on a single die. This paper presents GenerOS - a general asymmetric operating system kernel for multi-core systems. In principal, GenerOS partitions processing cores into application core, kernel core and interrupt core, each of which is dedicated to a specified function. In implementation, we conduct a delicate modification to Linux kernel and provide the same interface as Linux kernel so that GenerOS is compatible with legacy applications. The better performance of GenerOS mainly benefits from: (1) Applications run on their own cores with minimal interrupt and kernel support; (2) Every kernel service is encapsulated in to a serial process so that there will be fewer contentions than conventional symmetric kernel; (3) A slim schedule policy is used in the kernel core to support schedule between system calls with low overhead. Experiments with two typical workloads on 16-core AMD machine show that GenerOS behaves better than original Linux kernel when there are more processing cores (19.6% for TPC-H using oracle database management system and 42.8% for httperf using apache web server).

关键词： Operating systems Kernel Linux Scalability Data structures computer architecture Database systems Web server Multicore processing

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A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only) 10

A multi-FPGA based platform for emulating a 100m-transistor-...

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Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays

作者： Huandong Wang Xiang Gao Yunji Chen Dan Tang Weiwu Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781605589114

This paper describes a multi-FPGA based platform for emulating the Loongson-2G micro-processor on different mother boards. This platform is developed targeting at verification and evaluation of the Loongson-2G micro-processor, which is the next generation of Loongson-2 family, composed by one four-issue, out-of-order execution way 64-bit MIPS-compatible processor core named GS464, one 1M byte secondary Cache, one HyperTransport IO interface, one DDR2/3 memory interface and some other low speed IO interfaces. Most parts of this micro-process are mapped into the multi-FPGA based platform which consists two Vertex-5 330 FPGA chips. Semi-custom partitioning tactics within the entire design flow are developed to synthesize the whole designed into the multi-FPGA based platform. Modifications in architectural level are applied to the original architecture of the chip, in order to make it easy to be partitioned into two parts. High speed SEDES of HyperTransport IO link and DDR2/3 memory interface are emulated by using several clocks with different clock phases. To resolve the problem that hard to debug in FPGA system, a method by software probe with help of injected hardware modules in FPGA is developed and used to debug the problem causing by behavior mismatching between the ASIC ram block and the FPGA ram block. Some evaluation work on performance of Loongson-2G is done on this multi-FPGA based platform as pre-silicon test. To the authors' knowledge, there has been no previous work on such a big design used for verification and evaluation.

关键词： multi-fpga emulation loongson verification evaluation fpga

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On generation of a universal path candidate set containing testable long paths

On generation of a universal path candidate set containing t...

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IEEE International Test Conference

作者： Zijian He Tao Lv Huawei Li Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

We propose an efficient algorithm on generation of a universal path candidate set U that contains testable long paths for delay testing. Some strategies are presented to speed up the depth-first search procedure of U generation, targeting the reduction of checking times of sensitization criteria. Experimental results illustrate that our approach achieves an 8X speedup on average in comparison with the traditional depth-first search approach.

关键词： Automatic test pattern generation

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Using Index in the MapReduce Framework

Using Index in the MapReduce Framework

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International Asia-Pacific Web Conference (APWEB)

作者： Mingyuan An Yang Wang Weiping Wang Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China Institute of Computing Technology Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

MapReduce is a programming framework introduced by Google for large-scale data processing. It is usually used in a scan-centric fashion where all the data are split into blocks and Maps are generated for each block to scan and process the data in the block, then Reduces merge outputs from all the Maps. When a query intends to process only a subset of the data selected by a predicate, this brute-force method may cause extra I/O overhead spent on irrelevant data, and the overhead for initiating so many Maps may be non-trivial given that the actually interesting data for the query is comparatively small in volume. We propose an approach to integrate the index into the MapReduce execution in which only an appropriate number of Maps are generated, each of which accesses the data using an index. This approach incurs random I/O and remote access to data, so the overall performance depends on both system parameters and the query characteristics. We build a cost model for both this index access execution and the traditional full scan execution. This cost model can be used to choose between the two execution modes before executing a query. Experiments show that the index access execution can greatly outperform full scan execution when the selectivity of the predicate is low, and the cost model predicts the actual execution cost very well so can be used to determine the execution plan for a query.

关键词： Flash memory Indexing computer science Delay Tree data structures Energy efficiency Nonvolatile memory Costs Mechanical factors Energy storage

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