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An abstraction-guided simulation approach using Markov models for microprocessor verification 10

An abstraction-guided simulation approach using Markov model...

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： Tao Zhang Tao Lv Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9783981080162

In order to combine the power of simulation-based and formal techniques, semi-formal methods have been widely explored. Among these methods, abstraction-guided simulation is a quite promising one. In this paper, we propose an abstraction-guided simulation approach aiming to cover hard-to-reach states in functional verification of microprocessors. A Markov model is constructed utilizing the high level functional specification, i.e. ISA. Such model integrates vector correlations. Furthermore, several strategies utilizing abstraction information are proposed as an effective guidance to the test generation. Experimental results on two complex microprocessors show that our approach is more efficient in covering hard-to-reach states than similar methods. Comparing with some work with other intelligent engines, our approach could guarantee higher hit ratio of target states without efficiency loss.

关键词： Microprocessors Testing Computational modeling Engines Data mining computer simulation Power system modeling Laboratories computer architecture Instruction sets

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Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs 10

Accelerating Lightpath setup via broadcasting in binary-tree...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Binzhang Fu Yinhe Han Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9783981080162

In this paper, we propose a binary-tree waveguide connected Optical-Network-on-Chip (ONoC) to accelerate the establishment of the lightpath. By broadcasting the control data in the proposed power-efficient binary-tree waveguide, the maximal hops for establishing lightpath is reduced to two. With extensive simulations and analysis, we demonstrate that the proposed ONoC significantly reduces the setup time, and then the packet latency.

关键词： Optical waveguides Acceleration Broadcasting Network-on-a-chip Optical interconnections Delay Optical modulation Logic Microcavities Optical devices

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A general method to make multi-clock system deterministic 10

A general method to make multi-clock system deterministic

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Design, Automation and Test in Europe Conference and Exhibition

作者： Menghao Su Yunji Chen Xiang Gao Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9783981080162

Nondeterminism of multi-clock systems often complicates various system validation processes such as post silicon debugging and at-speed testing, which has brought many difficulties to system designers and testers. The major source of nondeterministic behaviors is clock domain crossing, because the clocks that determine the timing of events are sensitive to variations. In this paper, we propose a general method to eliminate the nondeterminism resulted from clock domain crossing. This method does not assume any specific relationship among the clocks. Instead, to adapt to various clock conditions, an automatic configuration procedure and a periodic error canceling mechanism, which only require trivial hardware support, are proposed by analyzing the deterministic boundaries theoretically. To demonstrate the applicability of our method in practice, we implement it on a FPGA platform. Experiment results validate that the performance loss brought by our method over conventional multi-clock FIFO is less than 2%.

关键词： Clocks Circuit testing Frequency synchronization Frequency estimation Debugging Hardware Field programmable gate arrays Silicon system testing Performance loss

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Diagnosis of multiple arbitrary faults with mask and reinforcement effect 10

Diagnosis of multiple arbitrary faults with mask and reinfor...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Jing Ye Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9783981080162

We propose a multiple-fault diagnosis method with high diagnosability, resolution, first-hit and short run time. The method has no assumption on fault models, thus can diagnose arbitrary faults. To cope with the multiple-fault mask and reinforcement effect, two key techniques of construction and scoring of fault-tuple equivalence trees are introduced to choose and rank the final candidate locations. Experimental results show that, when the circuits have 2 arbitrary faults, the average diagnosability and resolution are 98% and 0.95, respectively, with the best case 100% and 1.00. Moreover, in average, even when 21 arbitrary faults exist, our method can still identify 93% of them with the resolution 0.78, increased by 41% and 39% in comparison with the latest work where the diagnosability and resolution are 66% and 0.56. Finally, 96% of our top-ranked candidate locations are actual fault locations.

关键词： Fault diagnosis Circuit faults Testing Fault location Integrated circuit yield Time to market Costs Automatic test pattern generation Test pattern generators Laboratories

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An on-chip clock generation scheme for faster-than-at-speed delay testing 10

An on-chip clock generation scheme for faster-than-at-speed ...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Songwei Pei Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9783981080162

Faster-than-at-speed testing provides an effective way for detecting and debugging small delay defects in modern fabricated chips. However, the use of external automatic test equipment for faster-than-at-speed delay testing could be costly. In this paper, we present an on-chip clock generation scheme which facilitates faster-than-at-speed delay testing for both launch on capture and launch on shift test frameworks. The required test clock frequency with a high resolution can be obtained by specifying the information in the test patterns, which is then shifted into the delay control stages to configure the launch and capture clock generation circuit (LCCG) embedded on-chip. Similarly, the control information for selecting various test frameworks and clock signals can also be embedded in the test patterns. Experimental results are presented to validate the proposed scheme.

关键词： Clocks Delay Circuit testing Lab-on-a-chip Frequency Automatic testing Timing system testing Phase locked loops Circuit faults

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Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors

Address Remapping for Static NUCA in NoC-Based Degradable Ch...

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Pacific Rim International Symposium on Dependable Computing

作者： Ying Wang Lei Zhang Yinhe Han Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Large scale Chip-Multiprocessors (CMPs) generally employ Network-on-Chip (NoC) to connect the last level cache (LLC), which is generally organized as distributed NUCA (non-uniform cache access) arrays for scalability and efficiency. On the other hand, aggressive technology scaling induces severe reliability problems, causing on-chip components (e.g., cores, cache banks, routers) failure due to manufacture defects or on-line hardware faults. Typical degradable CMPs should possess the ability to work around defects by disabling faulty components. For static NUCA architecture, when cache banks attached to a computing node are disabled, however, certain physical address sections will no longer be accessible. Prior approaches such as sets reduction introduced in Intel Xeon processor 7100 series enable turning off cache banks by masking certain sets bits in physical address1, which greatly wastes cache capacity. In this paper, we propose to tackle the above problem in a finer granularity to restrict the capacity loss in NUCA cache. Cache accesses to isolated nodes are redirected based on the utility-driven address remapping scheme that reduces data blocks conflicts in fault-tolerant shared-LLC. We evaluate our technique using GEMS simulator. Experimental results show that address remapping achieves significant improvement over the conventional cache sizing scheme.

关键词： Tiles Nickel Hardware Fault tolerance Fault tolerant systems Prediction algorithms computer architecture

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Graph partition based path selection for testing of small delay defects 10

Graph partition based path selection for testing of small de...

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Asia and South Pacific Design Automation Conference

作者： Zijian He Tao Lv Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781605588377

Critical path selection plays an important role in testing of small delay defects (SDD). For some timing-balanced circuits, the numbers of candidate critical paths may be very large, and this will make Monte Carlo simulation based statistical timing analysis very inefficient. A fast path selection approach based on graph partition is proposed in this paper. First, a critical path graph (CPG) is generated to implicitly enumerate almost all candidate critical paths, and then the CPG is partitioned into several sub graphs which contain limited numbers of paths using two graph partition approaches. After that, Monte Carlo simulation is applied on each sub graph for path selection. At last, according to the partition topology of the CPG and path sets selected from each sub graph, a path set for the original CPG is generated using Union and Cartesian product operations for testing SDDs. Experimental results show that for circuits containing large numbers of candidate critical paths, the proposed path selection approach can reduce the CPU time significantly and maintain a higher probability of capturing delay failures compared to path selection methods based on general Monte Carlo simulation.

关键词： Timing Circuit testing Delay effects Sampling methods Monte Carlo methods Crosstalk system testing Laboratories Distributed computing computer architecture

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Known User Continuous Authentication system for Consumer Application Software

Known User Continuous Authentication System for Consumer App...

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Consumer Communications and Networking Conference, CCNC IEEE

作者： Ines Brosso Graca Bressan Wilson V. Ruggiero College of Computation and Informatics Mackenzie Presbyterian University Sao Paulo Brazil Laboratory of Computer Architecture and Networks Department of Computer and Digital System Engineering Polytechnic of São Paulo University Brazil

This paper presents KUCAS (Known User Continuous Authentication system), a work-in-progress security system, that has a continuous authentication mechanism of users/consumers. The KUCAS system makes use of environmental context information, users behavior analysis, the behavior theories of Skinner and the Mathematical Confidence of Dempster-Shafer Evidences Theory, that establishes trust levels to authenticate the user by his behavior analysis, during an application software, in a specific domain of the computer networks, in a period of time. The dynamics of enclosed management in this system compares the current behavior with the user's previous behaviors description and with the trust restrictions. In case of indications of changes in the user's behavior, the system provides the behavior analysis of the user using database restrictions information. If there are uncertainties and divergences, mechanisms of security and alert signals are triggered.

关键词： Authentication Application software Information security Information analysis Data security computer security Humans computer networks Peer to peer computing History

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A Continuous Authentication system Based on User Behavior Analysis

A Continuous Authentication System Based on User Behavior An...

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International Conference on Availability, Reliability and Security, ARES

作者： Ines Brosso Alessandro La Neve Graça Bressan Wilson Vicente Ruggiero College of Computation and Informatic Mackenzie Presbyterian University Sao Paulo SP Brazil Department of Electrical Engineering Centro Universitário da FEI Sao Paulo SP Brazil Laboratory of Computer Architecture and Networks Department of Computer and Digital System Engineering Polytechnic School of São Paulo University Brazil Laboratory of Computer Architecture and Networks Department of Computer and Digital System Engineering Polytechnic School of São Paulo University Brazil

ISBN: (纸本)9781424458790

This paper presents a continuous authentication system based on user behavior analysis that makes use of environmental context information, users' behavior analysis and Neuro-Fuzzy Logic. This system must be able to acquire information in context, making them into a computational environment. This information is the basis of user behavior. The system, based on the evidences of the behavior, establishes if it can trust the user or not. According to the user behavior, levels of trust are released, to access the application software. Weights are attributed in the fuzzyfication process, according to the rules that were previously established for the parameters which help to establish the evidences of behavioral trust, in its different degrees. The neuro-fuzzy logic allows that the user behavioral database be continuously updated, interacting with the fuzzyfication mechanism, so as to keep trust levels updated according to the user behavior, in a more accurate and faithful way.

关键词： Authentication Application software Information analysis Information security Logic Signal analysis Humans computer security computer networks Electronic mail

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High performance comparison-based sorting algorithm on many-core GPUs

High performance comparison-based sorting algorithm on many-...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Xiaochun Ye Dongrui Fan Wei Lin Nan Yuan Paolo Ienne Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China School of Computer and Communication Sciences Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland

Sorting is a kernel algorithm for a wide range of applications. In this paper, we present a new algorithm, GPU-Warpsort, to perform comparison-based parallel sort on Graphics Processing Units (GPUs). It mainly consists of a bitonic sort followed by a merge sort. Our algorithm achieves high performance by efficiently mapping the sorting tasks to GPU architectures. Firstly, we take advantage of the synchronous execution of threads in a warp to eliminate the barriers in bitonic sorting network. We also provide sufficient homogeneous parallel operations for all the threads within a warp to avoid branch divergence. Furthermore, we implement the merge sort efficiently by assigning each warp independent pairs of sequences to be merged and by exploiting totally coalesced global memory accesses to eliminate the bandwidth bottleneck. Our experimental results indicate that GPU-Warpsort works well on different kinds of input distributions, and it achieves up to 30% higher performance than previous optimized comparison-based GPU sorting algorithm on input sequences with millions of elements.

关键词： Sorting High performance computing Bandwidth Parallel architectures computer architecture Kernel Application software Multicore processing Graphics processing unit

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