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Asia and South Pacific Design Automation Conference

作者： Songwei Pei Ye Geng Huawei Li Jun Liu Song Jin Beijing University of Chemical Technology Beijing 100029 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing CN School of Computer and Information University of Technology Hefei China School of Electrical and Electronic Engineering North China Electric Power University Baoding China

ISBN: (纸本)9781479977932

On-chip faster-than-at-speed delay testing provides a promising way for small delay defect detection. However, the frequency of on-chip generated test clock would be impacted by process variations. Hence, it requires determining the actual frequency of generated test clock to ensure the effectiveness of faster-than-at-speed delay testing. In this paper, we present a novel test clock generation scheme, namely Enhanced LCCG, for faster-than-at-speed delay testing. In the proposed scheme, faster-than-at-speed test clock is firstly generated by configuring the corresponding control information specified in the test pattern into Enhanced LCCG. Then, by constructing oscillation paths and counting the corresponding oscillation iteration numbers, the actual frequency of test clock can be measured and calculated with high resolution. Experimental results are presented to validate the proposed method.

关键词： Delays Clocks Oscillators Testing Frequency measurement Logic gates

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Spatial throughput characterization in cognitive radio networks with threshold-based opportunistic spectrum access

Spatial throughput characterization in cognitive radio netwo...

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作者： Song, Xiaoshi Yin, Changchuan Liu, Danpu Zhang, Rui Beijing Key Laboratory of Network System Architecture and Convergence Beijing University of Posts and Telecommunications Beijing100876 China Department of Electrical and Computer Engineering National University of Singapore Singapore117576 Singapore

This paper studies the opportunistic spectrum access (OSA) of the secondary users in a large-scale overlay cognitive radio (CR) network. Two threshold-based OSA schemes, namely the primary receiver assisted (PRA) protocol and the primary transmitter assisted (PTA) protocol, are investigated. Under the PRA/PTA protocols, a secondary transmitter (ST) is allowed to access the spectrum only when the maximum signal power of the received beacons/pilots sent from the active primary receivers/transmitters (PRs/PTs) is lower than a certain threshold. To measure the resulting transmission opportunity for the secondary users by the proposed OSA protocols, the concept of spatial opportunity, which is defined as the probability that an arbitrary location in the primary network is detected as a spatial spectrum hole, is introduced and then evaluated by applying tools from stochastic geometry. Based on spatial opportunity, the coverage (non-outage transmission) performance in the overlay CR network is analyzed. With the obtained results of spatial opportunity and coverage probability, we finally characterize the spatial throughput, which is defined as the average spatial density of successful transmissions in the primary/secondary network, under the PRA and PTA protocols, respectively. © 1983-2012 IEEE.

关键词： Cognitive radio

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On-Chip Generating FPGA Configuration Bitstreams to Reduce Applycation-Independent Test Time

On-Chip Generating FPGA Configuration Bitstreams to Reduce A...

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The 4th International Workshop on Advanced Technologies in Programmable system on Chip(第四届片上可编程系统前沿技术研讨会)

作者： Da Wang Fei Wang Paolo Ienne Yu Hu Dongrui Fan Haigang Yang Key Laboratory of Computer System and Architecture Institute of Computing TechnologyCASBeijing100190China System on Programmable Chip Research DepartmentInstitute of ElectronicsCASBeijing100190China Processor Architecture LaboratoryEPFLLausanneSwitzerland

FPGA application independent test is very time-consuming due to repetitively loading of test configuration bitstreams into the FPGA and applying test *** shows that over 95%of FPGA application independent test time is spent on loading the test configuration ***,reducing the number of loading times could significantly reduce the FPGA test *** this paper,a new approach which can significantly reduce the FPGA test time will be *** this new approach,a configuration SRAM routing strategy is used first to enhance the correlation of the test bitstream configurations,then,on-chip test configuration generation structures are designed to transform a test bitstream configuration into other ones within limited *** results show that the proposed technique can at least reduce the configuration loading time by 81%,while getting 100%test *** hardware overhead is less than 1.2%upon the whole chip without any performance penalty.

关键词： FPGA test test configuration generation design-for-testability

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Test and repair flow for shared BISR in asynchronous multi-processors

Test and repair flow for shared BISR in asynchronous multi-p...

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20th IEEE International Symposium on Asynchronous Circuits and systems, ASYNC 2014

作者： Wang, Gang Wang, Xu Chen, Xinke Xue, Shuangbai Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100190 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Loongson Technology Corporation Limited Beijing 100190 China Shandong Eway Information and Technology Co. Ltd China

ISBN: (纸本)9781479937899

We present a hierarchical test and repair flow for shared BISR (Built-In Self-Repair) in asynchronous multi-processors. The flow partitions the memories local to a processor in groups and treats the groups as a whole when doing the repair. The flow runs automatically with few interventions except at the beginning stage. It can be used effectively for practical industrial test and repair. Its test time is as good as equivalent to that of parallel BISR, while its test power is substantially lower, about 40% that of parallel repair. It also has a superior repair rate, about 11-12% better compared to sequential and parallel BISR. © 2014 IEEE.

关键词： Repair

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Test and Repair Flow for Shared BISR in Asynchronous Multi-processors

Test and Repair Flow for Shared BISR in Asynchronous Multi-p...

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International Symposium on Advanced Research in Asynchronous Circuits and systems

作者： Gang Wang Xu Wang Xinke Chen Shuangbai Xue Key Laboratory of Computer System and Architecture Loongson Technology Corporation Limited Beijing Shandong Eway Information & Technology CO. Ltd

关键词： Maintenance engineering Program processors Synchronization Built-in self-test computers system-on-chip

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Dynamically tolerating and detecting asymmetric races

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2014年第8期51卷 1748-1763页

作者： Wang, Wenwen Wu, Chenggang Ratanaworabhan, Paruj Yuan, Xiang Wang, Zhenjiang Li, Jianjun Feng, Xiaobing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing100190 China University of Chinese Academy of Sciences Beijing100049 China Faculty of Engineering Kasetsart University Bangkok10900 Thailand

Asymmetric races are a common type of data races. They are triggered when a thread accesses a shared variable in a critical section, and another thread accesses the same shared variable not in any critical section, or in a critical section guarded by a different lock. Asymmetric races in multi-threaded programs are usually harmful. To solve the problem introduced by asymmetric races, ARace is proposed. ARace utilizes shared variable protecting and write buffer to dynamically tolerate and detect asymmetric races. Shared variable protecting is used to protect shared variables that are read-only and read-before-write in critical sections, and these shared variables should not be modified out of critical sections;write buffer is used to buffer the writing operations to shared variables in critical sections. ARace can not only tolerate asymmetric races triggered by shared variable accesses in and out of critical sections, but also detect asymmetric races triggered by shared variable accesses in concurrent critical sections. ARace can be directly applied to binary code and requires neither additional compiler support nor hardware support. In addition, an implementation based on dynamic binary instrumentation is also proposed. The experimental results demonstrate that ARace guarantees the tolerance and detection of asymmetric races while incurring acceptable performance and memory overhead.

关键词：非对称数据竞争容忍和检测写缓冲区页保护动态二进制插桩

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SeaBase: An Implementation of Cloud Database

SeaBase: An Implementation of Cloud Database

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International Conference on Semantics, Knowledge and Grid (SKG)

作者： Shusheng Guo Zimu Yuan Li Zha Zhiwei Xu State Key Laboratory of Computer System and Architecture University of Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781479967162

Cloud database usually refers to a database based on the cloud computing technology. However, as far as we know, pre-existing solutions of cloud database cannot integrate the data from multi-sourced heterogeneous databases, only supplying an isolated homogeneous database cluster. This paper presents a new implementation approach for cloud database: Sea Base, which integrates various data types into a unified one, based on the CCEVP(Cloud Computing-based Effective-Virtual-Physical) model. The results of our experiments show that Sea Base is feasible and practical.

关键词： Databases Cloud computing Computational modeling Data integration computers computer architecture Data models

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Multi-Cell Coordinated Scheduling and Power Allocation in Downlink LTE-A systems

Multi-Cell Coordinated Scheduling and Power Allocation in Do...

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IEEE Vehicular Technology Conference

作者： Jian Yu Geoffrey Ye Li Changchuan Yin Suwen Tang Xiaolong Zhu Beijing Key Laboratory of Network System Architecture and Convergence Beijing University of Posts and Telecommunications School of Electrical and Computer Engineering Georgia Institute of Technology Huawei Shanghai Research Institute

ISBN: (纸本)9781479944484

In this paper, we investigate multi-cell coordinated scheduling and power allocation in downlink long term evolution advanced (LTE-A) systems, where orthogonal frequency division multiple-access (OFDMA) is used. The proposed scheme performs joint scheduling, power allocation, and modulation and coding scheme (MCS) selection to maximize the overall weighted throughput with proportional fairness. Our scheme considers the practical constraints in LTE-A systems. Since the optimization problem is a combinatorial and non-convex one and is with high complexity, low-complexity and suboptimal algorithms are proposed, which separate the scheduling and power allocation into two subproblems. Simulation results show that the proposed scheme can improve the average system throughput by 10% and the 10th percentile throughput by 15% compared with the existing scheme.

关键词： Resource management Throughput Interference Signal to noise ratio Indexes Optimization Scheduling

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A business model for video transmission services using dynamic adaptation streaming over HTTP 9

A business model for video transmission services using dynam...

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9th Advanced International Conference on Telecommunications, AICT 2013

作者： Rodríguez, Demóstenes Zegarra Rosa, Renata Lopes Bressan, Graça Laboratory of Computer Architecture and Networks Computer and Digital System Engineering Department University of São Paulo São Paulo Brazil

ISBN: (纸本)9781612082790

A business model for video transmission services is proposed that uses the Dynamic Adaptation Streaming over HTTP (DASH) mechanism using different versions of the same video. These video versions are encoded using different parameters, such as spatial resolution or number of frames per second. The transmission of each video version depends on the capabilities of the network at the end user point. The business model proposed considers different costs for each version of video fragments transmitted. The costs of video resolution upgrade are predefined by the service provider and used during the video streaming. Also, in this model, the user can either accept or reject an upgrade. Subjective tests were performed using different spatial resolutions of the same video, in which the interest level of users to perform a video upgrade is evaluated. Furthermore, the network architecture of the proposed solution is presented and the technical feasibility to deploy the proposed solution in commercial networks is shown. As a consequence, the proposed solution can improve the earnings of the video service provider. Copyright © 2013 IARIA.

关键词： Video streaming

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Evaluating memory compression and deduplication

Evaluating memory compression and deduplication

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2013 IEEE 8th International Conference on Networking, architecture and Storage, NAS 2013

作者： Deng, Yuhui Song, Liangshan Huang, Xinyu Computer Science Department Jinan University Guangzhou 510632 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100190 China

ISBN: (纸本)9780769550343

Many programs require more RAM to hold their data than a typical computer has. Theoretically, both the compression and deduplication can trade the rich computing capacity for more available RAM space. This paper comprehensively evaluates the performance behaviour of memory compression and memory deduplication by using seven real memory traces. The experimental results give two implications: (1) Memory deduplication greatly outperforms memory block compression. (2) Fixed-size partition (FSP) achieves the best performance in contrast to Content-defined Chunking (CDC) and Sliding Block (SB). The optimal chunking size of FSP is equal to the size of a memory page. The analysis results in this paper should be able to provide useful insights for designing or implementing systems that require abundant memory resources to enhance the system performance. © 2013 IEEE.

关键词： Random access storage

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