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2022 IEEE Hot Chips 34 Symposium, HCS 2022

作者： Kwon, Miryeong Gouk, Donghyun Lee, Sangwon Jung, Myoungsoo Computer Architecture and Memory Systems Laboratory

Demonstration Video Link: https://***/watch?v=b5fZBESH1TM

ISBN: (数字)9781665460286

ISBN: (纸本)9781665460286

Demonstration Video Link: https://***/watch?v=b5fZBESH1TM

关键词： computer architecture Inference algorithms Graph neural networks Energy efficiency

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What’s Missing in Agile Hardware Design? Verification!

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Journal of computer Science & Technology 2023年第4期38卷 735-736页

作者： Babak Falsafi Parallel Systems Architecture Laboratory Institute of Computer and Communication SciencesSchool of Computer andCommunication SciencesEcole Polytechnique Fédérale de LausanneLausanneCH-1015Switzerland

Agile hardware design is an approach to developing hardware systems that draws inspiration from the principles and practices of agile software *** emphasizes collaboration,flexibility,iterative development,and quick adaptation to changing *** agile hardware design,the focus is on delivering functionalhardware systems in shorter development cycles while maintaining high-quality and customer *** particular,agile hardware design is of great interest in the open-source hardware ***-sourcehardware development—such as RISC-V—is at the forefront of initiatives to democratize hardware and drive innovation in chip design *** design is instrumental for the RISC-V community because it supportsrapid iteration,accommodates the evolving RISC-V standard and the addition of custom extensions,improvescommunity collaboration and time-to-market,and addresses the design challenges associated with complex architectural features.

关键词： hardware agile architectural

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DockerSSD: Containerized In-Storage Processing and Hardware Acceleration for Computational SSDs

DockerSSD: Containerized In-Storage Processing and Hardware ...

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IEEE Symposium on High-Performance computer architecture

作者： Donghyun Gouk Miryeong Kwon Hanyeoreum Bae Myoungsoo Jung Computer Architecture and Memory Systems Laboratory KAIST Panmnesia Inc

Processing data in storage is an energy-efficient solution to examine massive datasets. However, a general incarnation of such well-known task-offloading model in a real system is unfortunately unsuccessful due to not only poor performance but also many practical challenges, such as limited processing capabilities and high vulnerabilities at the storage-level. We propose DockerSSD, a fully flexible in-storage processing (ISP) model that can run a variety of applications near flash without their source-level modification. Specifically, it enables lightweight OS-level virtualization in modern SSDs, which allows the storage intelligence to be well harmonized with existing computing environment and makes ISP even faster. Instead of developing a vendor-specific ISP to offload, DockerSSD can reuse existing Docker images, create containers as a self-governing execution object in storage, and process data directly where they are in real-time. To this end, we design a new communication method and virtual firmware that operate together to download Docker images and manage their container execution without a change of the existing storage interface and runtime. We further accelerate ISP and reduce the execution latency by automating container-related network and I/O handling data paths over hardware. Our evaluation shows that DockerSSD is 2.0 × faster than state-of-the-art ISP models for workloads with a high volume of system calls or file accesses. Moreover, it demonstrates a reduction in power and energy consumption by 1.6 × and 2.3 × respectively.

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Early Execution for Soft Error Detection

Early Execution for Soft Error Detection

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International Conference on VLSI Design

作者： Raj Kumar Choudhary Janeel Patel Virendra Singh Computer Architecture and Dependable Systems Laboratory Indian Institute of Technology Bombay India

Single event upsets have made modern integrated circuits more susceptible to soft errors, making their operation less reliable. In order to detect induced computational faults, we propose a fault-tolerant, low-overhead microarchitecture that detects soft errors using temporal redundancy. The idea of introducing an Early Execution Unit (EXU) at the processor frontend has been explored by previous proposals in order to execute dynamic instructions with short dependency chains expeditiously for performance improvement. However, we observe that the functional units in the EXU are idle for a significant portion of the program execution duration. Our proposed microarchitecture utilises these inactive frontend functional units in order to re-execute dynamic instructions to ascertain computational correctness. A low-overhead backend verifier leverages idle resources for redundant execution using the proposed priority-based scheduling algorithm that interleaves program execution with re-execution for error detection. Our proposal provides exhaustive transient fault coverage while improving performance by 7.5% over an existing restricted OoO microarchitecture, Freeflow Core, delivering IPC close to that of an out-of-order baseline, while being $1.78 \times $ more energy-efficient than the involuted, power-hungry out-of-order design.

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Is the powersave governor really saving power?

Is the powersave governor really saving power?

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IEEE/ACM International Symposium on Cluster Computing and the Grid (CCGRID)

作者： Darong Huang Luis Costero David Atienza Embedded Systems Laboratory (ESL) EPFL Switzerland Dpto. of Computer Architecture and Automatics UCM Spain

ISBN: (数字)9798350395662

ISBN: (纸本)9798350395679

A frequency scaling governor is critical for the performance management of cloud servers, as it enhances energy efficiency and helps to control operational temperatures, thereby ensuring system reliability. However, our in-depth analysis of the application’s performance and Dynamic Voltage and Frequency Scaling (DVFS) actions, alongside assessments of server power consumption and operating temperature, indicates that existing Linux scaling governors often fall into non-optimal DVFS strategies, especially for cloud applications with varying workloads and requests. This shortfall comes from the misleading CPU load metrics, which fail to accurately capture the applications’ true performance requirements and demands. In this context, we introduce a novel scaling governor named GreenDVFS. First, it identifies the optimal frequencies for the application in a range of workload scenarios. Optimal frequencies are used to maintain application performance, reduce server power consumption, and maintain a balanced operating temperature in different workload scenarios. Furthermore, we design a long short-term memory (LSTM)-based time series methodology to detect the real-time workloads of cloud applications accurately and timely. Building on these foundations, the proposed method takes optimal DVFS actions, tailored for cloud applications under different workload conditions, to optimize performance, energy efficiency, and temperature. The experimental results highlight the effectiveness of the proposed GreenDVFS, with up to 18% savings in energy consumption and a 30% decrease in operational temperature by comparing against the default Linux governor, all while not compromising the application’s performance. Such improvements help to optimize cloud computing operations for enhanced efficiency and sustainability.

关键词： Cloud computing Runtime Power demand Temperature Linux Time series analysis Energy efficiency Real-time systems Temperature control Servers

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ERrOR: Improving Performance and Fault Tolerance Using Early Execution

ERrOR: Improving Performance and Fault Tolerance Using Early...

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IEEE Symposium on On-Line Testing (IOLTS)

作者： Raj Kumar Choudhary Janeel Patel Virendra Singh Computer Architecture and Dependable Systems Laboratory Indian Institute of Technology Bombay India

Contemporary integrated circuits are becoming increasingly susceptible to soft errors due to single-event upsets, effectively decreasing the reliability of operation. In this paper, we propose the ERrOR microarchitecture, that detects soft errors in processor operation using temporal redundancy with minimal hardware overhead. Previous proposals have explored the idea of introducing an Early Execution Unit (EXU) at the processor frontend in order to expeditiously execute dynamic instructions with short dependency chains for performance improvement. However, we observe that the functional units in the EXU are idle for a significant fraction of the program execution duration. ERrOR leverages these inactive frontend functional units to re-execute dynamic instructions for the purpose of error detection. A lightweight verifier introduced at the backend makes use of idle resources for redundant execution by interleaving program execution with re-execution for error detection. ERrOR provides exhaustive transient fault coverage while improving performance by 7.5% over an existing restricted OoO microarchitecture, Freeflow Core.

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GraphTensor: Comprehensive GNN-Acceleration Framework for Efficient Parallel Processing of Massive Datasets

GraphTensor: Comprehensive GNN-Acceleration Framework for Ef...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Junhyeok Jang Miryeong Kwon Donghyun Gouk Hanyeoreum Bae Myoungsoo Jung Computer Architecture and Memory Systems Laboratory Korea Advanced Institute of Science and Technology (KAIST)

We present GraphTensor, a comprehensive open-source framework that supports efficient parallel neural network processing on large graphs. GraphTensor offers a set of easy-to-use programming primitives that appreciate both graph and neural network execution behaviors from the beginning (graph sampling) to the end (dense data processing). Our framework runs diverse graph neural network (GNN) models in a destination-centric, feature-wise manner, which can significantly shorten training execution times in a GPU. In addition, GraphTensor rearranges multiple GNN kernels based on their system hyperparameters in a self-governing manner, thereby reducing the processing dimensionality and the latencies further. From the end-to-end execution viewpoint, GraphTensor significantly shortens the service-level GNN latency by applying pipeline parallelism for efficient graph dataset preprocessing. Our evaluation shows that GraphTensor exhibits 1.4× better training performance than emerging GNN frameworks under the execution of large-scale, real-world graph workloads. For the end-to-end services, GraphTensor reduces training latencies of an advanced version of the GNN frameworks (optimized for multi-threaded graph sampling) by 2.4×, on average.

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Geospatial exploration of geothermal reservoirs in the Souss Massa regions of the anti-atlas and Moroccan Sahara

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Materials Today: Proceedings 2022年 72卷 3911-3926页

作者： El Bouazouli, Abderrahim Baidder, Lahssen Bahi, Hicham Abdehamid, Fadil Rhouzlane, Said Moussaoui, Rabia Oukrich, Nadia Baite, Wissal Hlal, Mohammed Laboratory of Geosciences Faculty of Sciences Aïn Chock University Hassan II of Casablanca Morocco School of Architecture Planning and Design Mohammed VI Polytechnic University Benguerir Morocco Morocco Polytechnic School of Montreal Canada Laboratory of Industrial Equipe Architecture de Systems ENSEM Morocco research laboratory in computer science and education the mohammedia school of engineering Rabat Morocco Laboratory of Industrial Engineering Sciences and Technologies Faculty Sultan Moulay Slimane University Beni Mellal Morocco laboratory Dynamics of arid environments Mohamed Premier University Oujda Morocco

Geothermal reservoirs refer to any heat stored, naturally, in the earth's crust;it is considered as resource coming from a natural complex depending on the geological, geophysical aspect and territories geochemistry. Although this natural resource remains distinguished by his characters to be a renewable, ecological, universal and sustainable mining energy, it stills not, yet, sufficiently exploitable worldwide (El Bouazouli et al., 2020). The same finding was brought up in Moroccan context, despite the presence of some hot resources and capitalizable scientific research to develop this potential. Prospecting for underground geothermal resources is an expensive project that deserves to mobilize scientific and technical methods in order to overcome this risky impasse. Thus, Geomatics has been used, drawing on Remote Sensing for geo-spatial exploration in order to guide prospecting through the development of geothermal deposits potential maps at very low and medium depth on Moroccan territories (El Bouazouli et al., 2019). Furthermore, we explore smart tools to support short and long-term decision-making in terms of creating of clean energy mix and complementary mining energy as well as investment in energy exploration operations. And, as an experiment, we chose for this study, areas distributed mainly in the Moroccan Sahara and the Souss Massa Region, known, probably, by a potentially high geothermal gradient, and therefore constituting geothermal energy reservoirs. As for the exploration methodology adopted, it consists in processing of the imageries: LANDSAT 8, MODIS AND ASTER, in order to extract exploitation indices such as the surface temperature, the layer of lineaments and cracks density, and evidence of hydrothermal alteration that may indicate geothermal activity. The correlation between these three factors, will lead us to conclude that the Moroccan Sahara area is considered as one of the most potential geothermal reservoir areas in Morocco. In short, the a

关键词： Decision making

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FADE: Forecasting for Anomaly Detection on ECG

arXiv

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arXiv 2025年

作者： Ruiz-Barroso, Paula Castro, Francisco M. Miranda, José Constantinescu, Denisa-Andreea Atienza, David Guil, Nicolás Department of Computer Architecture University of Málaga Malaga29071 Spain Embedded Systems Laboratory the École Polytechnique Fédérale of Lausanne Lausanne Switzerland

Background and Objective: Cardiovascular diseases, a leading cause of noncommunicable disease-related deaths, require early and accurate detection to improve patient outcomes. Taking advantage of advances in machine learning and deep learning, multiple approaches have been proposed in the literature to address the challenge of detecting ECG anomalies. Typically, these methods are based on the manual interpretation of ECG signals, which is time consuming and depends on the expertise of healthcare professionals. The objective of this work is to propose a deep learning system, FADE, designed for normal ECG forecasting and anomaly detection, which reduces the need for extensive labeled datasets and manual interpretation. Methods: We propose FADE, a deep learning system designed for normal ECG forecasting, trained in a self-supervised manner with a novel morphological inspired loss function, that can be used for anomaly detection. Unlike conventional models that learn from labeled anomalous ECG waveforms, our approach predicts the future of normal ECG signals, thus avoiding the need for extensive labeled datasets. Using a novel distance function to compare forecasted ECG signals with actual sensor data, our method effectively identifies cardiac anomalies. Additionally, this approach can be adapted to new contexts (e.g., different sensors, patients, etc.) through domain adaptation techniques. To evaluate our proposal, we performed a set of experiments using two publicly available datasets: MIT-BIH NSR and MIT-BIH Arrythmia. Results: The results demonstrate that our system achieves an average accuracy of 83.84% in anomaly detection, while correctly classifying normal ECG signals with an accuracy of 85.46%. Conclusions: Our proposed approach exhibited superior performance in the early detection of cardiac anomalies in ECG signals, surpassing previous methods that predominantly identify a limited range of anomalies. FADE effectively detects both abnormal heartbeats and arrhy

关键词： Electrocardiography

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Affine-NoC: Multi-ring NoCs exploiting long physical links

Affine-NoC: Multi-ring NoCs exploiting long physical links

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International Workshop on Network on Chip architectures, NoCArc

作者： Enrique Vallejo Evangelos Mageiropoulos Nikolaos Chrysos Manolis G.H. Katevenis Computer Science Dept. Universidad de Cantabria Spain Santander Spain Computer Architecture and VLSI Systems (CARV) Laboratory Foundation for Research and Technology – Hellas (FORTH) Heraklion Greece

ISBN: (数字)9798331506421

ISBN: (纸本)9798331506438

Routerless multi-ring proposals are low-cost NoCs that employ multiple independent rings, avoiding any crossbars or arbitration mechanisms. Their complexity lies on the selection of the set of rings to connect all the nodes. Previous proposals result in unbalanced designs with high hop *** work introduces Affine-NoC, a balanced routerless NoC based on a novel arrangement of rings derived from the Affine Plane. Affine-NoC exploits express channels to connect distant processing elements, allowing for a completely balanced layout of the set of rings and a reduction in average distance and diameter without sacrificing bisection *** shows that Affine-NoC presents a balanced design with a low number of rings per node and reduced complexity, similar cost to previous proposals in terms of aggregated link length, while it simplifies the multiplex units and reduces the hop count. Simulation results show that Affine-NoC reduces hop count and average latency by 76% and 20.5% respectively compared to previous designs, it reduces deflections by 27% and avoids unfairness, making it a feasible alternative for multi-ring routerless NoCs.

关键词： Multiplexing Network topology Flow production systems Simulation Layout computer architecture Complexity theory Topology Proposals Logic

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