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Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA 21st

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Hardware-Accelerated Event-Graph Neural Networks for Low-La...

21st International Symposium on Applied Reconfigurable Computing, ARC 2025

作者： Nakano, Hiroshi Blachut, Krzysztof Jeziorek, Kamil Wzorek, Piotr Dampfhoffer, Manon Mesquida, Thomas Nishi, Hiroaki Kryjak, Tomasz Dalgaty, Thomas Graduate School of Science and Technology Keio University Tokyo Japan Embedded Vision Systems Group Computer Vision Laboratory AGH University of Krakow Krakow Poland CEA-List Université Grenoble Alpes Grenoble France

ISBN: (纸本)9783031879944

As the quantities of data recorded by embedded edge sensors grow, so too does the need for intelligent local processing. Such data often comes in the form of time-series signals, based on which real-time predictions can be made locally using an AI model. However, a hardware-software approach capable of making low-latency predictions with low power consumption is required. In this paper, we present a hardware implementation of an event-graph neural network for time-series classification. We leverage an artificial cochlea model to convert the input time-series signals into a sparse event-data format that allows the event-graph to drastically reduce the number of calculations relative to other AI methods. We implemented the design on a SoC FPGA and applied it to the real-time processing of the Spiking Heidelberg Digits (SHD) dataset to benchmark our approach against competitive solutions. Our method achieves a floating-point accuracy of 92.7% on the SHD dataset for the base model, which is only 2.4% and 2% less than the state-of-the-art models with over 10× and 67× fewer model parameters, respectively. It also outperforms FPGA-based spiking neural network implementations by 19.3% and 4.5%, achieving 92.3% accuracy for the quantised model while using fewer computational resources and reducing latency. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： event-based audio processing FPGA graph convolutional neural networks dynamic audio sensor artificial cochlea

Real-Time Multi-Object Tracking using YOLOv8 and SORT on a SoC FPGA

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arXiv 2025年

作者： Danilowicz, Michal Kryjak, Tomasz Embedded Vision Systems Group Computer Vision Laboratory Department of Automatic Control and Robotics AGH University of Krakow Poland

关键词： System-on-chip

FADE: Forecasting for Anomaly Detection on ECG

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arXiv 2025年

作者： Ruiz-Barroso, Paula Castro, Francisco M. Miranda, José Constantinescu, Denisa-Andreea Atienza, David Guil, Nicolás Department of Computer Architecture University of Málaga Malaga29071 Spain Embedded Systems Laboratory the École Polytechnique Fédérale of Lausanne Lausanne Switzerland

Background and Objective: Cardiovascular diseases, a leading cause of noncommunicable disease-related deaths, require early and accurate detection to improve patient outcomes. Taking advantage of advances in machine learning and deep learning, multiple approaches have been proposed in the literature to address the challenge of detecting ECG anomalies. Typically, these methods are based on the manual interpretation of ECG signals, which is time consuming and depends on the expertise of healthcare professionals. The objective of this work is to propose a deep learning system, FADE, designed for normal ECG forecasting and anomaly detection, which reduces the need for extensive labeled datasets and manual interpretation. Methods: We propose FADE, a deep learning system designed for normal ECG forecasting, trained in a self-supervised manner with a novel morphological inspired loss function, that can be used for anomaly detection. Unlike conventional models that learn from labeled anomalous ECG waveforms, our approach predicts the future of normal ECG signals, thus avoiding the need for extensive labeled datasets. Using a novel distance function to compare forecasted ECG signals with actual sensor data, our method effectively identifies cardiac anomalies. Additionally, this approach can be adapted to new contexts (e.g., different sensors, patients, etc.) through domain adaptation techniques. To evaluate our proposal, we performed a set of experiments using two publicly available datasets: MIT-BIH NSR and MIT-BIH Arrythmia. Results: The results demonstrate that our system achieves an average accuracy of 83.84% in anomaly detection, while correctly classifying normal ECG signals with an accuracy of 85.46%. Conclusions: Our proposed approach exhibited superior performance in the early detection of cardiac anomalies in ECG signals, surpassing previous methods that predominantly identify a limited range of anomalies. FADE effectively detects both abnormal heartbeats and arrhy

关键词： Electrocardiography

Vision-based automatic fruit counting with UAV

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arXiv 2025年

作者： Szolc, Hubert Wasala, Mateusz Mietla, Remigiusz Iwicki, Kacper Kryjak, Tomasz Embedded Vision Systems Group Computer Vision Laboratory Department of Automatic Control and Robotics AGH University of Krakow al. Mickiewicza 30 Krakow30–059 Poland

The use of unmanned aerial vehicles (UAVs) for smart agriculture is becoming increasingly popular. This is evidenced by recent scientific works, as well as the various competitions organised on this topic. Therefore, in this work we present a system for automatic fruit counting using UAVs. To detect them, our solution uses a vision algorithm that processes streams from an RGB camera and a depth sensor using classical image operations. Our system also allows the planning and execution of flight trajectories, taking into account the minimisation of flight time and distance covered. We tested the proposed solution in simulation and obtained an average score of 87.27/100 points from a total of 500 missions. We also submitted it to the UAV Competition organised as part of the ICUAS 2024 conference, where we achieved an average score of 84.83/100 points, placing 6th in a field of 23 teams and advancing to the finals. © 2025, CC BY.

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Corrigendum to "Hyperledger sawtooth based supplychain traceability system for counterfeit drugs" [Comput. Ind. Eng. 190 (2024) 110021] (computers & Industrial Engineering (2024) 190, (S0360835224001426), (10.1016/***.2024.110021))

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computers and Industrial Engineering 2025年 204卷

作者： Nawaz, Anum Wang, Liguan Irfan, Muhammad Westerlund, Tomi Shanghai Key Laboratory of Intelligent Information Processing School of Computer Science Fudan University Shanghai China Turku Intelligent and Embedded Robotic Systems Lab Faculty of Technology University of Turku Finland

关键词：

Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA

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arXiv 2025年

作者： Nakano, Hiroshi Blachut, Krzysztof Jeziorek, Kamil Wzorek, Piotr Dampfhoffer, Manon Mesquida, Thomas Nishi, Hiroaki Kryjak, Tomasz Dalgaty, Thomas Graduate School of Science and Technology Keio University Tokyo Japan Embedded Vision Systems Group Computer Vision Laboratory AGH University of Krakow Poland CEA-List Université Grenoble Alpes Grenoble France

关键词： Graph neural networks

A weakly supervised pavement crack segmentation based on adversarial learning and transformers

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Multimedia systems 2025年第3期31卷 1-21页

作者： Apedo, Yvon Tao, Huanjie School of Computer Science Northwestern Polytechnical University Xi’an People’s Republic of China Engineering and Research Center of Embedded Systems Integration (Northwestern Polytechnical University) Ministry of Education Xi’an People’s Republic of China National Engineering Laboratory for Integrated Aero-Space-Ground-Ocean Big Data Application Technology Xi’an People’s Republic of China

While pixel-level crack segmentation has demonstrated significant potential in infrastructure inspections, its reliance on detailed annotations poses challenges for widespread adoption due to the time-consuming and expensive nature of such labeling. In response, weakly supervised crack segmentation has garnered attention as it eliminates the need for pixel-level annotations. However, existing methods, primarily based on class activation maps (CAM), involve complex training processes and suffer from poor performance due to misalignment between CAM-generated labels and the true target in the image. To address these challenges, we propose a weakly supervised approach for crack segmentation that simultaneously generates synthetic crack images and performs segmentation through adversarial learning. Unlike traditional methods that rely on coarse labels, our approach leverages synthetic crack images with corresponding labels, effectively eliminating issues of misalignment and noisy pseudo-labels. Our method introduces an encoder-decoder architecture for the segmentation model, incorporating a Transformer-based Feature Enhancement module (TFE) in the encoder. This module is specifically designed to capture long-range dependencies and efficiently integrate both high- and low-level features. Additionally, the model includes a Hilo block to extract both high- and low-frequency information from the images, along with a Progressive Shrinking Decoder (PSD) to aggregate and refine adjacent feature maps. Extensive experiments were conducted, and our model achieved an ODS of 67.12% on the CrackForest dataset, 60.11% on the Crack500 dataset, and 44.80% on the AEL dataset. These results demonstrate that our model outperforms several existing weakly supervised pavement segmentation methods across these datasets.

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Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28nm RISC-V-based SoC

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IEEE Transactions on Nuclear Science 2025年

作者： Rogenmoser, Michael Wiese, Philip Forlin, Bruno Endres Gurkaynak, Frank K. Rech, Paolo Menicucci, Alessandra Ottavi, Marco Benini, Luca Integrated Systems Laboratory ETH Zurich Switzerland Computer Architecture for Embedded Systems University of Twente Netherlands Department of Industrial Engineering University of Trento Italy Delft University of Technology Department of Space Engineering Netherlands University of Rome Department of Electronic Engineering Tor Vergata Italy Information Engineering at the University of Bologna Department of Electrical Electronic Italy

RISC-V-based fault-tolerant system-on-chip (SoC) designs are critical for the new generation of automotive and space SoC architectures. However, reliability assessment requires characterization under controlled radiation doses to accurately quantify the fault tolerance of the fabricated designs. This work analyzes the Trikarenos design, a SoC implemented in TSMC 28nm, for single event upset (SEU) vulnerability under atmospheric neutron and 200MeV proton radiation, comparing these results to simulation-based fault injection. All faults in error correction codes (ECC) protected memory are corrected by a scrubber, showing an estimated cross-section per bit of up to 1.09 × 10−14 cm2 bit−1. Furthermore, the triple-core lockstep (TCLS) mechanism implemented in Trikarenos is validated and is shown to correct errors affecting a cross-section up to 3.23 × 10−11 cm2, with the remaining uncorrectable vulnerability below 5.36 × 10−12 cm2. When augmenting the experimental analysis of fabricated chips with gate-level fault injection in simulation, 99.10% of injections into the SoC produced correct results, while 100% of injections in the TCLS-protected cores were handled *** 12.28%of all injected faults leading to a TCLS recovery, this indicates an approximate effective flip-flop cross-section of up to 1.28 × 10−14 cm2/FF. © 1963-2012 IEEE.

关键词： Radiation damage

Test Time Minimization for Hybrid BIST of Core-Based systems

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Journal of computer Science & Technology 2006年第6期21卷 907-912页

作者： Gert Jervan Petru Eles Zebo Peng Raimund Ubar Maksim Jenihhin Embedded Systems Laboratory (ESLAB) Linkoeing University Sweden Department of Computer Engineering Tallinn University of Technology Estonia

This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. In this paper we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach cmploys a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions.

关键词： SoC self-test hybrid BIST