BGP, the de-facto inter-domain routing protocol, is well-known for its complexity in configuring correct behaviour. This stems from the fact that the protocol is policy-based. Despite best practice and guidelines, it ...
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The long and increasing test application time for modular core-based system-on-chips is a major problem, and many approaches have been developed to deal with the problem. Different from previous approaches, where it i...
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In everyday life, sense of humor usually comes through the production of jokes. The ability to be funny or to be amused by a joke is not an easy task for human because of cultural background and their capacity to perc...
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There was widespread agreement that Communication can be a struggle for some deaf and hearing impaired people. The big breakthrough is the development of sign language (SL) which has enabled this category of people to...
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This article studies the scheduling problem of a set of tasks with time or data constraints on a number of identical processors with full connections. We present an algorithm, in which a set of static schedule lists c...
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The Tellez-Molina-Villa (TMV) algorithm is a new defuzzification method for interval type-2 fuzzy systems. It is based on found the mean trajectory of any interval type-2 fuzzy set. With the mean trajectory we pretend...
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Reservation Tables (RTs) have long been used to detect conflicts between operations that simultaneously access the same architectural resource. Traditionally, these RTs have been specified explicitly by the designer. ...
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ISBN:
(纸本)076950356X
Reservation Tables (RTs) have long been used to detect conflicts between operations that simultaneously access the same architectural resource. Traditionally, these RTs have been specified explicitly by the designer. However, the increasing complexity of modern processors makes the manual specification of RTs cumbersome and error-prone. Furthermore, manual specification of such conflict information is infeasible for supporting rapid architectural exploration. In this paper we present an algorithm to automatically generate RTs from a high-level processor description, with the goal of avoiding manual specification of RTs, resulting in more concise architectural specifications and also supporting faster turn-around time in Design Space Exploration. We demonstrate the utility of our approach on a set of experiments using the TI C6201 VLIW DSP and DLX processor architectures, and a suite of multimedia and scientific applications.
Literature indicates that spatial diversity can be utilized to compensate channel uncertainties such as multipath fading. Therefore, in this paper, spatial diversity is exploited for locating stationary and mobile obj...
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Many researchers and vendors are exploiting the increasing number of transistors to build chip multiprocessors (CMPs) by partitioning a chip into multiple simple ILP cores. As in traditional multiprocessors, CMPs extr...
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