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An efficient local address generation for the block-cyclic distribution 3

An efficient local address generation for the block-cyclic d...

引用

3rd International Conference on Algorithms and Architectures for parallel Processing, ICA3PP 1997

作者： Kwon, Oh-Young Kim, Tae-Geun Han, Tack-Don Yang, Sung-Bong Kim, Shin-Dug Distributed Computing Lab. Systems Engineering Research Institute 1 Ueun-dong Yusong-gu Taejon305-333 Korea Republic of Parallel Processing System Laboratory Dept. of Computer Science Yonsei University Seoul120-749 Korea Republic of

ISBN: (纸本)0780342291

In order to generate local addresses for an array section A(l:h:s) with block-cyclic distribution, an efficient compiling method is required. In this paper, two local address generation methods for the block-cyclic distribution are presented. One is a simple local address generation method that is modified from the virtual-block scheme. The other is a linear-time ΔM table construction method. The array elements of A(l:h:s) to be accessed at run-time build up a family of lines. By using the equation of the lines, a ΔM table can be generated in O(k) time. Experimental results show that a simple local address generation method has poor performance but a linear-time ΔM table generation method is faster than other algorithms in ΔM table generation time and access time for 10,000 array elements. © 1997 IEEE.

关键词： Virtual addresses

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A comparison of parallel approaches for algebraic factorization in logic synthesis

A comparison of parallel approaches for algebraic factorizat...

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International Symposium on parallel Processing

作者： S. Roy P. Banerjee Coordinated Science Laboratory University of Illinois Urbana IL USA Center for Parallel & Distributed Computing Northwestern University Evanston IL USA

Algebraic factorization is an extremely important part of any logic synthesis system, but it is computationally expensive. Hence, it is important to look at parallel processing to speed up the procedure. This paper presents three different parallel algorithms for algebraic factorization. The first algorithm uses circuit replication and uses a divide-and-conquer strategy. A second algorithm uses totally independent factorization on different circuit partitions with no interactions among the partitions. A third algorithm represents a compromise between the two approaches. It uses a novel L-shaped partitioning strategy which provides some interaction among the rectangles obtained in various partitions. For a large circuit like ex1010, the last algorithm runs 11.5 times faster over the sequential kernel extraction algorithms of the SIS sequential circuit synthesis system on six processors with less than 0.2% degradation in quality of the results.

关键词： Logic functions Circuit synthesis Partitioning algorithms Network synthesis Contracts parallel processing Laser sintering Degradation Logic design Sequential circuits

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An L-shaped partitioning-based algebraic factorization algorithm

An L-shaped partitioning-based algebraic factorization algor...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： S. Roy P. Banerjee Coordinated Science Laboratory University of Illinois Urbana IL USA Center for Parallel and Distributed Computing Northwestern University Evanston IL USA

Algebraic factorization is an extremely important part of any logic synthesis system but it is computationally expensive. Hence it is important to speed it up. The paper presents an algorithm to speedup the factorization by partitioning the circuit and performing factorizations on the sub-circuits. The approach clusters the entries of the co-kernel cube matrix into dense blocks using a novel L-shaped partitioning and searches these blocks for kernels. The L-shaped approach runs up to five times faster than the kernel extraction routine in SIS.

关键词： Partitioning algorithms Kernel Circuit synthesis distributed computing Network synthesis Contracts Logic functions Concurrent computing Clustering algorithms Logic design

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An efficient local address generation for the block-cyclic distribution

An efficient local address generation for the block-cyclic d...

引用

IEEE International Conference on Algorithms and Architectures for parallel Processing (ICAP)

作者： Oh-Young Kwon Tae-Geun Kim Tack-Don Han Sung-Bong Yang Shin-Dug Kim Distributed Computing Laboratory Systems Engineering Research Institute Taejon South Korea Parallel Processing System Laboratory Department of Computer Science Yonsei University Seoul South Korea

ISBN: (纸本)0780342291

In order to generate local addresses for an array section A(l:h:s) with block-cyclic distribution, an efficient compiling method is required. In this paper, two local address generation methods for the block-cyclic distribution are presented. One is a simple local address generation method that is modified from the virtual-block scheme. The other is a linear-time /spl Delta/M table construction method. The array elements of A(l:h:s) to be accessed at run-time build up a family of lines. By using the equation of the lines, a /spl Delta/M table can be generated in O(k) time. Experimental results show that a simple local address generation method has poor performance but a linear-time /spl Delta/M table generation method is faster than other algorithms in /spl Delta/M table generation time and access time for 10,000 array elements.

关键词： Runtime Equations distributed computing Systems engineering and theory parallel processing Laboratories Computer science parallel languages Upper bound Automata

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parallel global routing algorithms for standard cells

Parallel global routing algorithms for standard cells

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International Symposium on parallel Processing

作者： Z. Xing J. Chandy P. Banerjee Computer and Systems Research Laboratory University of Illinois Urbana IL USA Cadence Design Systems Chelmsford MA USA Center for Parallel and Distributed Computing Northwestern University Evanston IL USA

In this paper, we propose three different parallel algorithms based on a state-of-the-art global router called TimberWolfSC. The parallel algorithms have been implemented by using the Message Passing Interface (MPI), and have been evaluated on a wide range of parallel platforms such as the Sun SparcCenter 1000 and the Intel Paragon. Our experimental results show good speedups and qualities from two of these parallel algorithms. We have been able to reduce runtimes of some circuits from half an hour to 5 minutes, obtained speedups of about 4.0 to 5.0 on 8 processors, with less than 2-3% degradation of quality of the solutions.

关键词： Routing parallel algorithms distributed computing Message passing Pins Wire Contracts Concurrent computing Laboratories Sun

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Unique sets oriented partitioning of nested loops with non-uniform dependences 25

Unique sets oriented partitioning of nested loops with non-u...

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25th International Conference on parallel Processing, ICPP 1996

作者： Ju, Jialin Chaudhary, V. Parallel and Distributed Computing Laboratory Wayne State University DetroitMI United States

ISBN: (纸本)081867623X

Although many methods exist for nested loop partitioning, most of them perform poorly when parallelizing loops with non-uniform dependences. This paper addresses the issue of parallelizing nested loops with non-uniform dependences. The approach is based on convex hull theory, which has adequate information to handle non-uniform dependences. We introduce the concept of Complete Dependence Convex Hull, unique head and tail sets and abstract the dependence information into these sets. These sets form the basis of the iteration space partitions. The properties of the unique head and tail sets are derived using convex hull theory. Depending on the relative placement of these unique sets, the partitioning problem is grouped into several cases. Several partitioning schemes are also suggested for implementing the technique. Preliminary implementation results of the scheme on the Cray J916 and comparison with other schemes show a dramatic improvement in performance. © 1996 IEEE.

关键词： Computational geometry

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Unique sets oriented partitioning of nested loops with non-uniform dependences

Unique sets oriented partitioning of nested loops with non-u...

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International Conference on parallel Processing (ICPP)

作者： Jialin Ju V. Chaudhary Parallel and Distributed Computing Laboratory Wayne State University Detroit MI USA

关键词： Tail parallel processing distributed computing Laboratories Sparse matrices Contracts Processor scheduling Indium tin oxide Tiles

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Design and evaluation of an environment APE for automatic parallelization of programs

Design and evaluation of an environment APE for automatic pa...

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International Symposium on parallel Architectures, Algorithms and Networks (ISPAN)

作者： V. Chaudhary Chengzhong Xu S. Roy Jialin Ju V. Sinha Laiwu Luo Parallel and Distributed Computing Laboratory Department of Electrical and Computer Engineering Wayne State University MI USA

In this paper, we present the design and evaluation of a compiler system, called APE, for automatic parallelization of scientific and engineering applications on distributed memory computers. APE is built on top of SUIF compiler. It extends SUIF with capabilities in parallelizing loops with non-uniform cross-iteration dependencies, and in handling loops that have indirect access patterns. We have evaluated the effectiveness of SUIF with several CFD test codes, and found that SUIF handles uniform loops over dense and regular data structures very well. For non-uniform loops, an innovative and efficient parallelization approach based on convex theory have been proposed and is being implemented. We have also presented a class of scalable algorithms for parallel distribution and redistribution of unstructured data structures during parallelizing irregular loops.

关键词： Program processors distributed computing Concurrent computing Computational fluid dynamics Data structures Quantum computing Programming profession parallel processing Design engineering Optimizing compilers

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parallel image processing in heterogeneous computing network systems

Parallel image processing in heterogeneous computing network...

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IEEE International Conference on Image Processing

作者： P. Chalermwat N. Alexandridis P. Piamsa-Nga M. O'Connell Parallel and Distributed Computing Laboratory George Washington University Washington D.C. DC USA

We present a uniform construct of parallel programming for a set of image processing tasks based on our distributed computing primitive (DCP) concept. Our target architecture is a heterogeneous computing network system consisting of various high performance workstations connected through a local area network. We show that DCP has advantages over non-primitive PVM-based parallel approaches in three aspects: ease-of-use, automation, and optimization.

关键词： Image processing Computer networks Concurrent computing parallel programming distributed computing Computer architecture High performance computing Workstations Local area networks Automation

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parallel algorithms for force directed scheduling of flattened and hierarchical signal flow graphs

Parallel algorithms for force directed scheduling of flatten...

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： P. Prabhakaran P. Banerjee Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana IL USA Center for Parallel and Distributed Computing Department of Electrical and Computer Engineering Northwestern University Evanston IL USA

In this paper we present some novel algorithms for scheduling hierarchical signal flow graphs in the domain of high-level synthesis. There are several key contributions of this paper. First, we develop a novel extension of the force directed scheduling problem which naturally handles loops and conditionals by coming up with a scheme of scheduling hierarchical signal flow graphs. Second, we develop three new parallel algorithms for the scheduling problem. Third, our parallel algorithms are portable across a wide range of parallel platforms. We report results on a set of high-level synthesis benchmarks on 8-processor SGI Challenge and a network of 4 SUN SPARCstation5 work stations. Finally, while some parallel algorithms for VLSI CAD reported by earlier researchers have reported a loss of qualities of results, our parallel algorithms produce exactly the same results as the sequential algorithms on which they are based.

关键词： parallel algorithms Flow graphs Processor scheduling Concurrent computing Scheduling algorithm Contracts Cost function Broadcasting

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