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A standard cell global routing algorithm with net selection for over-the-cell routing

ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE 1995年第12期78卷 102-115页

作者： Koide, T Suzuki, T Wakabayashi, S Yoshida, N Member Faculty of Engineering Hiroshima University Higashi-Hiroshima Japan 724 Associate Member Shin'ichi:Wakabayashi received his B.E. degree in Electrical Engineering and his M.E. and Ph.D. degrees in Systems Engineering from Hiroshima University in 1979 1981 and 1984 respectively. He was a Researcher at Tokyo Research Laboratory IBM Japan Ltd. in 1984-1988. Since 1988 he has been an Associate Professor on the Faculty of Engineering Hiroshima University. His research interests include VLSI CAD combinatorial optimization parallel and distributed algorithms and theory of computing. Dr. Wakabayashi is a member of the Institute of Electrical and Electronics Engineers the Association for Computing Machinery the Institute of Electronics Information and Communication Engineers and the Information Processing Society of Japan. Members

In the detailed routing for VLSI standard cell layout design, the over-the-cell channel routing, which utilizes the over-the-cell legion as the routing region, has been proposed. In this design method, after determining the net assignment to each channel in the global routing step, the track assignment both in channel and on over-the-cell regions is performed by an over-the-cell channel router. However, conventional global routing algorithms do not assume over-the-cell channel routing but conventional channel routing, Therefore, the minimization of channel density does not always successfully lead to the minimization of the final channel height. This paper presents a new global Touting method for standard cell layouts to determine global routes for each net in both channel and over-the-cell regions simultaneously. The standard cell layout design system GLORIA based on the proposed algorithm is developed, and the experimental results compared with the conventional global routing method that performs the over-the-cell channel routing after global-routing with TimberWolf-SC4.2c are reported. Experimental results showed that the proposed routing algorithm can route about 18.4 percent fewer number of tracks than the conventional routing method, and the effectiveness of the proposed method is shown. The experimental results of applying the proposed method to the three-layer routing layout model also are presented.

关键词： standard cell layout design CAD global routing over-the-cell routing

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parallel AND distributed TLM COMPUTATION WITH SIGNAL-PROCESSING FOR ELECTROMAGNETIC-FIELD MODELING

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INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS 1995年第3-4期8卷 169-185页

作者： SO, PPM ESWARAPPA, C HOEFER, WJR NSERC/MPR Teltech Research Chair in RF Engineering Department of Electrical and Computer Engineering University of Victoria Victoria British Columbia V8W 3P6 Canada Poman So received his B.Sc. degree in computer science and physics from the University of Toronto Toronto Onatario Canada in 1985. He obtained his B.A. Sc. and M.A.Sc. degrees in electrical engineering (summa cum laude) from the University of Ottawa Ottawa Ontario Canada in 1987 and 1989 respectively. Mr So was a research engineer in the University of Ottawa from January 1989 to October 1991 his research interests included CAD techniques of microwave circuits and numerical methods for electromagnetic wave modelling. He specialized in the development of electromagnetic engineering CAD software and successfully implemented a number of electromagnetic wave simulators based on the two-dimensional and three-dimensional transmission-line matrix methods. From August 1990 to February 1991 he accompanied Professor W. J. R. Hoefer to Rome Italy and Sophia Antiopolas France. During that time he implemented a parallel version of the 3D-TLM simulator for the CM-2 Connection Machine using C-Star and X Windows Library. He is a research engineer and a Ph.D. student at the University of Victoria Victoria British Columbia Canada. He ported the 2D- and 3D-TLM simulators to DECmpp 1200 massively parallel computer using MPL C and C++. He also combined OSA90/hope a commercially available microwave CAD program with a 2D-TLM simulation module for geometry optimization using the Datapipe technique of OSA90/hope. Recently he has developed a distributed client-server computing technique for the TLM method this technique could accelerate the TLM simulation by more than an order of magnitude. Channabasappa Eswarappa received the M.Tech. degree in electrical engineering from the Indian Institute of Technology Kanpur India in 1983 and Ph. D. degree from the University of Ottawa Canada in 1990. He worked as an Assistant Executive Engineer and later as

This paper describes the implementation of transmission-line matrix (TLM) method algorithms on a massively parallel computer (DECmpp 12000), the technique of distributed computing in the UNIX environment, and the combination of TLM analysis with Prony's method as well as with autoregressive moving average (ARMA) digital signal processing for electromagnetic field modelling. By combining these advanced computation techniques, typical electromagnetic field modelling of microwave structures by TLM analysis can be accelerated by a few orders of magnitude.

关键词： Mathematical models

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A comparative study of star graphs and rotator graphs

A comparative study of star graphs and rotator graphs

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23rd International Conference on parallel Processing, ICPP 1994

作者： Ponnuswamy, Subburajan Chaudhary, Vipin Parallel and Distributed Computing Laboratory Dept. of ECE Wayne State University Detroit MI 48202 United States

ISBN: (纸本)0849324939

Star graph is an extensively studied Cayley graph, considered to be an attractive alternative to the popular binary cube. The rotator graphs are a set of directed Cayley graphs introduced recently. In this paper we compare the structural and algorithmic aspects of star graphs with that of rotator graphs. In the process we present some new results for star graphs and rotator graphs. We present a formula for the number of nodes at any distance from the identity permutation in star graphs. The minimum bisection width of star and rotator graphs is obtained. Partitioning and fault tolerant parameters for both star and rotator graphs are analyzed. The node disjoint parallel paths and hence the upper bound on the fault diameter of rotator graphs are presented. We compare the minimal path routing in star and rotator graphs using simulation results. © 1994 IEEE.

关键词： Directed graphs

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A Comparative Study of Star Graphs and Rotator Graphs

A Comparative Study of Star Graphs and Rotator Graphs

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International Conference on parallel Processing (ICPP)

作者： Subburajan Ponnuswamy Vipin Chaudhary Parallel and Distributed Computing Laboratory Department of ECE Wayne State University Detroit MI USA

关键词： Routing Fault tolerance Tin parallel processing distributed computing Laboratories Delay Computational modeling Upper bound Multiprocessing systems

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Embedding of cycles in rotator and incomplete rotator graphs

Embedding of cycles in rotator and incomplete rotator graphs

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International Symposium on parallel and distributed Processing (IPDPS)

作者： S. Ponnuswamy V. Chaudhary Parallel and Distributed Computing Laboratory Department of Electrical and Computer Engineering Wayne State University Detroit MI USA

Symmetric directed Cayley graphs called rotator graphs have been proposed recently in the literature. In addition to a lower diameter and average distance compared to the star graph, hypercube, and k-ary n-cubes, these rotator graphs also have a rich cyclic structure. We identify a variety of disjoint cycles in rotator graphs. An efficient algorithm for Hamiltonian cycles in rotator graphs is presented. This algorithm uses a basic sequence of four generators repeatedly with generators of higher order in between, to obtain Hamiltonian cycle in any n-rotator graph. We study the embedding of undirected cycles and directed cycles in rotator graphs. We also prove that the incomplete rotator graph obtained from the rotator graph is Hamiltonian. The embedding of undirected rings in rotator graphs is shown to have a low average dilation.< >

关键词： Multiprocessor interconnection networks distributed computing parallel processing Algorithm design and analysis Laboratories Concurrent computing Hypercubes Optical fiber communication Very large scale integration Protocols

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Contention sensitive fault-tolerant routing algorithms for hypercubes

Contention sensitive fault-tolerant routing algorithms for h...

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International Symposium on parallel Architectures, Algorithms and Networks (ISPAN)

作者： R. Srinivasan V. Chaudhary S.M. Mahmud Parallel and Distributed Computing Laboratory Department of Electrical and Computer Engineering Wayne State University Detroit MI USA

We present two new fault tolerant routing algorithms for hypercubes. The first algorithm requires only local knowledge of the faults whereas the second algorithm requires global knowledge. Unlike previous fault tolerant routing algorithms, our algorithms take into consideration the dynamic conditions (link contention) of the network. We have shown that checking for dynamic conditions in fault tolerant algorithms is essential. Performance evaluation by extensive simulation of our algorithms and other fault tolerant routing algorithms show that ours are better than previous algorithms by as much as 50%; and 500%; in time and space, respectively. We also observed that global information about the location of faults does not give us additional benefit. This observation is true regardless of the consideration of the dynamic conditions in the network.< >

关键词： Fault tolerance Routing Hypercubes Telecommunication traffic distributed computing Laboratories Network topology Scalability Hardware Adaptive algorithm

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Minimum dependence distance tiling of nested loops with non-uniform dependences

Minimum dependence distance tiling of nested loops with non-...

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International Symposium on parallel and distributed Processing (IPDPS)

作者： S. Punyamurtula V. Chaudhary Parallel and Distributed Computing Laboratory Department of Electrical and Computer Engineering Wayne State University Detroit MI USA Wayne State University

We address the problem of partitioning nested loops with non-uniform (irregular) dependence vectors. Although many methods exist for nested loop partitioning, most of these perform poorly when parallelizing nested loops with irregular dependencies. We apply the results of classical convex theory and principles of linear programming to iteration spaces and show the correspondence between minimum dependence distance computation and iteration space tiling. The cross-iteration dependencies are analyzed by forming an Integer Dependence Convex Hull (IDCH). A simple way to compute minimum dependence distances from the dependence distance vectors of the extreme points of the IDCH is presented. Using these minimum dependence distances the iteration space can be tiled. Iterations in a tile can be executed in parallel and the tiles can be executed with proper synchronization. We demonstrate that our technique gives much better speedup and extracts more parallelism than the existing techniques.< >

关键词： Tiles distributed computing Concurrent computing Vectors Linear programming parallel processing Laboratories Sequential analysis Data analysis Data mining

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MANIPULATIONS OF OCTREES AND QUADTREES ON MULTIPROCESSORS

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International Journal of Pattern Recognition and Artificial Intelligence 1994年第2期8卷 439-455页

作者： VIPIN CHAUDHARY K. KUMARI P. ARUNACHALAM J.K. AGGARWAL Parallel and Distributed Computing Laboratory Department of Electrical and Computer Engineering Wayne State University Detroit MI 48202 USA Sun Microsystems 2820 Orchard Parkway San Jose CA 95134 USA Computer and Vision Research Center Department of Electrical and Computer Engineering University of Texas at Austin Austin Texas 78712–1084 USA

Octrees offer a powerful means for representing and manipulating 3-D objects. This paper presents an implementation of octree manipulations using a new approach on a shared memory architecture. Octrees are hierarchical data structures used to model 3-D objects. The manipulation of these data structures involves performing independent computations on each node of the octree. Octrees are much easier to deal with than other forms of representations used to model 3-D objects especially where extensive manipulations are involved. When these operations are distributed among multiple processing elements (PEs) and executed simultaneously, a significant speedup may be achieved. Manipulations such as a complement, a union, an intersection and other operations such as finding the volume and centroid which this paper describes are implemented on the Sequent Balance multiprocessor. In this approach the PEs are allocated dynamically, resulting in a uniform load balancing among them. The experimental results presented illustrate the feasibility of the approach. Although this evaluation has been originally done for shared memory machines, it will provide insight for the evaluation of other architectures.

关键词： Shared memory architecture dynamic allocation union intersection orthogonal views

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Mapping algorithms for permutation networks

Mapping algorithms for permutation networks

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： V. Chaudhary Parallel and Distributed Computing Laboratory Department of Electrical and Computer Engineering Wayne State University Detroit MI USA

The mapping problem arises when the dependency structure of a parallel algorithm differs from the interconnection of processors in the intended parallel computer (topological variation) or, when the number of processes required by the algorithm exceeds the number of processors available in the computer (cardinality variation). The problem discussed in this paper is to identify a distributed computing environment that best optimizes the objective function for the given problem. Distinct network permutations may result in equivalent process permutation depending upon the mapping of processes onto the processors. In this paper we study the permuting properties of dynamic interconnection networks taking process mapping into consideration. A uniform group theoretic representation for interconnection networks is developed. Finally, an algorithm to evaluate the number of passes required by an interconnection network to realize a given mapping is presented.< >

关键词： Multiprocessor interconnection networks distributed computing Concurrent computing parallel algorithms Multiprocessing systems Laboratories Costs Delay effects Routing

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Embedding of meshes on rotator graphs

Embedding of meshes on rotator graphs

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： S. Ponnuswamy V. Chaudhary Dept. of Electr. & Comput. Eng. Wayne State Univ. Detroit MI USA Parallel and Distributed Computing Laboratory Department of Electrical and Computer Engineering Wayne State University Detroit MI USA

A set of directed permutation graphs called rotator graphs were proposed as an alternative to the star and pancake graphs for multiprocessor interconnection networks. The rotator graphs have a smaller diameter than star and pancake graphs for the same number of nodes, while sharing the properties of star, pancake, and binary hypercubes like maximal fault tolerance, partitionability, etc. In this paper we develop a class of algorithms for recognizing undirected mesh structures in n-rotator graphs. The average dilation of the embeddings are very low as compared to the dilation of the embedding. These embeddings will be very useful for regular computations with bi-directional requirements, in addition to the irregular computations in n-rotator graphs. Most of the results presented here equally apply to another set of directed Cayley graphs, the cycle prefix digraphs.< >

关键词： Multiprocessor interconnection networks Hypercubes Bidirectional control Concurrent computing Fault tolerance Embedded computing Routing Application software Sorting Computer vision

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