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NAND flash testing: A preliminary study on actual defects

NAND flash testing: A preliminary study on actual defects

引用

IEEE International Test Conference

作者： P.-D. Mauroux A. Virazel A. Bosio L. Dilillo P. Girard S. Pravossoudovitch B. Godard Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier Université Montpellier Montpellier France Libraries and Design Tools Department Embedded Non-Volatile Memory Group ATMEL Rousset Rousset France

embedded flash memories are dominated by the NOR architecture but NAND is becoming more and more adopted due to its high storage capacity. This paper presents a preliminary study on actual defects in NAND array.

ISBN: (纸本)9781424448685

关键词： Testing nonvolatile memory Flash memory Logic Uniform resource locators Robots libraries Manufacturing processes Frequency Fault detection

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Hierarchical Code Correction and Reliability Management in embedded nor Flash Memories

Hierarchical Code Correction and Reliability Management in E...

引用

IEEE European Test Symposium (ETS)

作者： Benoit Godard Jean-Michel Daga Lionel Torres Gilles Sassatelli Libraries and Design Tools Department-Embedded Non-Volatile Memory Group Rousset France Laboratoire d'coInformatique de Robotique et deUMR5506 CNRS Université de Montpellier II Montpellier France

The framework of this article lies in the dynamic management of the reliability in NOR embedded Flash memories (eFlash). The main objective is to build a new reliability management scheme and to predict its efficiency to improve the eFlash reliability using error correction code and redundancy. The originality of the proposed approach relies on the use of a dedicated error correcting code well suited to NOR flash memories operational conditions. This code, named hierarchical code, improves the correction capabilities with a minimal impact on performance and area. The proposed solution furthermore enables selecting different built-in self strategies allowing to tune reliability strategies to the targeted application domain.

关键词： Flash memory Error correction codes Redundancy Decoding Testing nonvolatile memory Error correction System-on-a-chip Random access memory Integrated circuit yield

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A concurrent approach for testing address decoder faults in eFlash memories

A concurrent approach for testing address decoder faults in ...

引用

2007 IEEE International Test Conference, ITC

作者： Ginez, O. Girard, P. Landrault, C. Pravossoudovitch, S. Virazel, A. Daga, J.-M. Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier - LIRMM Université de Montpellier II CNRS 161 rue Ada 34392 Montpellier Cedex 5 France ATMEL Rousset Libraries and Design Tools Department Embedded Non-Volatile Memory Group 13106 Rousset Cedex France

ISBN: (纸本)1424411289

The evolution of System-on-Chip (SoC) designs involves the development of non-volatile memory technologies like Flash. As any kind of memories, embedded Flash (eFlash) can be subjected to complex functional faults that are related to their particular technological process and to their integration density. In this paper, we address a major issue during eFlash testing, namely the test of Address decoder Faults (AFs), which is generally very time consuming with ad-hoc solutions presently used in industry. In the first part of the paper, we show the impact of AFs on the functional behavior of an eFlash. Next, we use an analogy with RAM memory testing to classify AFs with respect to their functional behavior. We then obtain AFs acting either as stuck-at faults or as state coupling faults. In the fourth part of the paper, we propose a concurrent approach for testing AFs acting on either the word line decoder or the bit line decoder. The proposed approach allows using a minimal number of programming operations during test application. Finally, we propose a compaction procedure to further reduce the test time of AFs. As a result, huge reductions in test time can be achieved;experiments on a 4 Mbits eFlash have shown that a test time reduction factor of 34x can be obtained when compared to the global eFlash test flow presently used in industry. An additional important feature of the proposed strategy is that it allows testing 100% of other critical faults in eFlashs (stuck-at, transition and state coupling faults) beside full coverage of AFs. © 2007 IEEE.

关键词： Flash memory

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Evaluation of design for Reliability Techniques in embedded Flash Memories

Evaluation of Design for Reliability Techniques in Embedded ...

引用

design, Automation and Test in Europe Conference and Exhibition

作者： Benoit Godard Jean-Michel Daga Lionel Torres Gilles Sassatelli Libraries and Design Tools Department Embedded Non-Volatile Memory Group Rousset France Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier-LIRMM Université de Montpellier Montpellier France

ISBN: (纸本)9783981080124

nonvolatile flash memories are becoming more and more popular in systems-on-chip (SoC). embedded flash (eFlash) memories are based on the well-known floating-gate transistor concept. The reliability of such type of technology is a growing up issue for embedded systems; endurance and retention are of course the main features to analyze. To enhance memory reliability current eFlash memories designs use techniques such as error correction code (ECC), redundancy or threshold voltage (V T ) analysis. In this paper, a memory model to evaluate the reliability of eFlash memory arrays under distinct enhancement schemes is developed

关键词： Flash memory Error correction codes Redundancy nonvolatile memory Random access memory Error correction Threshold voltage Silicon libraries Robots

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Architecture for Highly Reliable embedded Flash Memories

Architecture for Highly Reliable Embedded Flash Memories

引用

IEEE design and Diagnostics of Electronic Circuits and Systems (DDECS)

作者： Benoit Godard Jean-Michel Daga Lionel Torres Gilles Sassatelli Montpellier Laboratory of Computer Science Robotics and Microelectronics-LIRMMUMR5506 CNRS Université de Montpellier II Montpellier France Libraries and Design Tools Department-Embedded Non-Volatile Memory Group ATMEL Rousset Rousset France

non-volatile embedded Flash (eFlash) memories are very popular in Systems-on-a-Chip (SoC). These memories are based on the well-known floating gate concept. While densities and quality constraints are increasing, the reliability becomes a growing up issue. For eFlash memories, endurance and retention issues are at the root of reliability losses. To improve reliability, eFlash memories designs usually use techniques such as Error Correcting Codes (ECC), Redundancy and Threshold Voltage (V T ) Analysis. In this paper, an implementation of these techniques is proposed through an architecture. Thanks to eFlash specificity, the correction capacity is improved via a double correction scheme. Additionally, each time an operation is performed on a memory element, a smart reliability management tracks online errors and weak bits. When few issues in a word catch out the double error correction scheme, a refresh and repair with low redundancy process is engaged.

关键词： Flash memory Error correction codes Redundancy nonvolatile memory Error correction System-on-a-chip Computer architecture Threshold voltage Logic memory architecture

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A concurrent approach for testing address decoder faults in eFlash memories

A concurrent approach for testing address decoder faults in ...

引用

IEEE International Test Conference

作者： O. Ginez P. Girard C. Landrault S. Pravossoudovitch A. Virazel J.-M. Daga Laboratoire dInformatique de Robotique et de Microélectronique de Montpellier LIRMMCNRS Université de Montpellier II Montpellier France ATMEL Rousset Libraries and Design Tools Department Embedded Non-Volatile Memory Group France

The evolution of system-on-chip (SoC) designs involves the development of non-volatile memory technologies like Flash. As any kind of memories, embedded Flash (eFlash) can be subjected to complex functional faults that are related to their particular technological process and to their integration density. In this paper, we address a major issue during eFlash testing, namely the test of Address decoder Faults (AFs), which is generally very time consuming with ad-hoc solutions presently used in industry. In the first part of the paper, we show the impact of AFs on the functional behavior of an eFlash. Next, we use an analogy with RAM memory testing to classify AFs with respect to their functional behavior. We then obtain AFs acting either as stuck-at faults or as state coupling faults. In the fourth part of the paper, we propose a concurrent approach for testing AFs acting on either the word line decoder or the bit line decoder. The proposed approach allows using a minimal number of programming operations during test application. Finally, we propose a compaction procedure to further reduce the test time of AFs. As a result, huge reductions in test time can be achieved; experiments on a 4 Mbits eFlash have shown that a test time reduction factor of 34x can be obtained when compared to the global eFlash test flow presently used in industry. An additional important feature of the proposed strategy is that it allows testing 100% of other critical faults in eFlashs (stuck-at, transition and state coupling faults) beside full coverage of AFs.

关键词： Testing Decoding nonvolatile memory Failure analysis Random access memory Uniform resource locators System-on-a-chip Flash memory Robots libraries

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Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for D...

引用

IEEE European Test Symposium (ETS)

作者： O. Ginez J.-M. Daga P. Girard C. Landrault S. Pravossoudovitch A. Virazel Laboratoire d'Informatique de Robotique et de Microélectronique de MontpellierCNRS Université de Montpellier II Montpellier France Libraries and Design Tools Department ATMEL Rousset Embedded Non-Volatile Memory Group Rousset France

The embedded flash technology can be subject to complex defects creating functional faults. In this paper, we describe the different steps in the electrical modeling of 2T-FLOTOX core-cells for a good understanding of failure mechanisms. First, we present a first order electrical model of 2T-FLOTOX core-cells which is characterized and compared with silicon data measurements based on the ATMEL 0.15 mum eFlash technology. Next, we propose a study of resistive defect injections in eFlash memories to show the relevance of the proposed simulation model. At the end of the paper, a table summarizes the functional fault models for different resistive defect configurations and experimental set-ups. According to these first results and with additional analysis of actual defects presented in [1] we are then able to enhance existing test solutions for eFlash testing.

关键词： Predictive models Testing nonvolatile memory Silicon Logic Uniform resource locators System-on-a-chip Performance analysis Robots libraries

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Retention and Reliability Problems in embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window

Retention and Reliability Problems in Embedded Flash Memorie...

引用

VLSI Test Symposium

作者： O. Ginez J.-M. Daga P. Girard C. Landrault S. Pravossoudovitch A. Virazel Laboratoire d'Informatique de Robotique et de Microélectronique de MontpellierCNRS Université de Montpellier II Montpellier France Libraries and Design Tools Department Embedded Non-Volatile Memory Gr ATMEL Rousset Rousset France

The evolution of system-on-chip (SoC) designs involves the development of non-volatile memory technologies like flash. embedded flash (eFlash) memories are based on the floating-gate transistor concept and can be subject to complex hard defects creating functional faults. In this paper, the authors analyze the impact of a defective tunnel window oxide thickness. The authors show that this defective oxide thickness impacts erase or/and write operations as well as the retention and reliability of the eFlash. The proposed solution to detect such a defective oxide consists in using the voltage disturbance due to the coupling phenomenon existing between bit lines. This particular defective mechanism can be modeled as a coupling fault, especially a state coupling fault. Based on this analysis, the authors propose a test solution that uses two checkerboard patterns; checkerboard pattern (CKB) and its complement (CKBI). The authors show that these two patterns have to be applied by using a parallel programming approach, which allows to increase the coupling phenomenon and thus the voltage disturbance

关键词： Flash memory nonvolatile memory Parallel programming Tunneling Uniform resource locators Logic testing Voltage control Random access memory Robots libraries

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embedded flash testing: overview and perspectives

Embedded flash testing: overview and perspectives

引用

International Conference on design and Technology of Integrated Systems in Nanoscale Era (DTIS)

作者： O. Ginez J.-M. Daga P. Girard C. Landrault S. Pravossoudovitch A. Virazel Laboratoire dInformatique de Robotique et de Microélectronique de Montpellier Université de Montpellier II Montpellier France ATMEL Rousset-Libraries and Design Tools Department Embedded Non-Volatile Memory Group Rousset France

关键词： nonvolatile memory Tunneling Flash memory Parallel programming Uniform resource locators Failure analysis Random access memory Logic testing Voltage control Variable structure systems

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An overview of failure mechanisms in embedded flash memories

An overview of failure mechanisms in embedded flash memories

引用

VLSI Test Symposium

作者： O. Ginez J.M. Daga M. Combe P. Girard C. Landrault S. Pravossoudovitch A. Virazel Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier-LIRMMCNRS Université de Montpellier II France Libraries and Design Tools Department Embedded Non-Volatile Memory Group ATMEL Rousset Rousset France

non-volatile flash memories are becoming more and more popular for system-on-chip design (SoC). embedded flash (eFlash) memories are based on the floating-gate transistor concept and can be subject to complex hard defects creating functional faults. Studies of realistic failure mechanisms and their associated fault models are the first mandatory step before providing efficient and practical new test methods. In this paper, we present an analysis made on actual failures occurring in 2T FLOTOX cells of 0.15mum NOR-based embedded flash structure

关键词： Failure analysis nonvolatile memory Flash memory Testing Uniform resource locators System-on-a-chip Silicon Random access memory Voltage libraries

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