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Free-Space Laser Communications XXXVII 2025

作者： Carlson, Robert Chterev, Ianko Sefler, George Rose, Todd S. Nee, Phil Klimcak, Charles Gupta, Shantanu Freeman, Wade Wayne, David Cote, Nick Kepler, Daniel Butterfield, Michael Rahimzadeh, Stephanos The Aerospace Corp United States Smart Logic United States Space Development Agency United States Modern Technology Solutions Inc. United States GoLion LLC Russia

ISBN: (纸本)9781510684584

The SDA OCT Standard v.3.1.0 defines a 2500 Mbaud NRZ on-off keyed (OOK) waveform for space-space link connectivity between SDA pLEO satellites separated by up to 5500 km. For longer range 20,000 km MEO-LEO links, the new SDA OCT Standard v.4.0.0 specifies a burst mode Manchester waveform for closing these links at lower data rates. The burst mode waveform uses the same clock/slot rate as specified in v.3.1.0 thereby enabling backward compatibility with previous versions of SDA optical terminals. The data rate is set by the duty cycle of the bursts. Manchester-coded data, along with forward error correction, consistent with v.3.1.0, aids with clock and data recovery. Forward and return link modes, BM12 and BM16 with a 1/12 and 1/16 duty cycle, provide User rates of 48.9 Mbps and 36.7 Mbps, respectively. Testing was performed with an upgraded burst-mode SDA reference modem (COMET), and we summarize testing end-to-end of a laboratory proof-of-concept incorporating a laser, modulator, EDFA TX and RX amplifiers, and optical receiver. © 2025 SPIE.

关键词： Clocks

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Device Design Guidelines to Boost up AC Performance of CFET (Complementary Field-Effect-Transistor)-Based Inverter

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2025年

作者： Lim, Jaehyuk Han, Donghwan Sung, Juho Yoon, Seokchan Kang, Sanghyun Kim, Gwon Baac, Hyoung Won Shin, Changhwan Sungkyunkwan University Department of Electrical and Computer Engineering Suwon16419 Korea Republic of Korea University School of Electrical Engineering Seoul02841 Korea Republic of Samsung Electronics Semiconductor Research and Development Center Logic Technology Development Team Hwaseong18448 Korea Republic of

Complementary Field-Effect Transistors (CFETs) have emerged as promising candidates for next-generation semiconductor devices. CFETs feature a structure with an NMOS (or PMOS) transistor at the bottom and a transistor of the opposite type at the top. CFETs can be classified into Fin-CFETs or GAA-CFETs based on their channel structure. In this study, we compare and analyze these two devices to determine which structure is more favorable for device scaling and which device exhibits better performance per unit area. For a reliable analysis, the threshold voltage was adjusted to be the same for all devices. Initially, to compare the DC performance, the on-state drive currents in both linear mode and saturation mode operations were extracted and compared from the IDS-vs.-VGS input-transfer characteristics. Subsequently, CMOS inverters were constructed to compare their AC performance. Six parameters were extracted and compared: high-to-low propagation delay (tpHL), falling time (tf), low-to-high propagation delay (tpLH), rising time (tr), overshoot voltage (Vov), and undershoot voltage (Vund). Based on the results, we suggest which CFET structure is more suitable for device scaling. © 1982-2012 IEEE.

关键词： CMOS integrated circuits

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Arsenic dimer (As2+) Lightly Doped Drain(LDD)implantation study for 20nm logic device development

Arsenic dimer (As2+) Lightly Doped Drain(LDD)implantation st...

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作者： Sun, Hao Li, Yong Zhang, Shuai Xie, Xinyun Cai, Gorge Zhou, Zuyuan Shi, Xuejie He, Yonggen Shi, Weimin Ju, Jianhua Chen, Larry Yu, Shaofeng School of Materials Science and Eng Shanghai University 200072 China Logic Technology and Development Center SMIC 201203 China

ISBN: (纸本)9781607685395

Process variation presents a significant challenge to future scaling of VLSI technology. Junction depth scaling with small Vth variation is required for the 45 nm technology node and beyond. Variations in MOSFET characteristics due to random dopant fluctuation (RDF) may become a fundamental limit to device scaling and circuit complexity. Arsenic dimer (As2+) implant has been used for the formation of ultra-shallow source drain extensions for NMOS transistors below 45nm, CMOS logic process. As Dimer requires only half the dose and twice the energy of equivalent As+ so it is more favorable for much lower energy (+ implantation. However, arsenic dimer implantation showed better Vth mismatch performance than conventional As+ implantation. © 2014 The Electrochemical Society.

关键词： Capacitance

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The high-k solution

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IEEE SPECTRUM 2007年第10期44卷 29-35页

作者： Bohr, Mark T. Chau, Robert S. Ghani, Tahir Mistry, Kaizad Process architecture and integration Intel Transistor Transistor technology and integration Logic and technology development group

The article reports on Intel's latest Core 2 microprocessors, also known as Penryn. This latest innovation from Intel is based on a 45-nanometer CMOS process technology. It is expected to run cooler and faster than previous microprocessors. The development of the Penryn was accomplished through a major breakthrough on the way the gate stack was manufactured. Intel developers experienced a shortage of atoms when the transistor's gate oxide reached a thickness of only 5 atoms. They developed the high-k plus metal gate transistors to address the limitations they faced with the silicon dioxide insulators. Penryn processors can have as much as 820 million transistors, versions of which can be used for different devices including mobile, desktop, server applications, and workstations.

关键词： MICROPROCESSORS TRANSISTORS SILICA METAL insulator semiconductors ATOMS NANOSTRUCTURED materials TECHNOlogicAL innovations COMPUTERS

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A Bandgap Diode-Based Voltage Band Detection Circuit With Fast Response Time and Low Vmin on Intel 4 logic technology

IEEE Solid-State Circuits Letters

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IEEE Solid-State Circuits Letters 2025年

作者： Bhatt, Kedar Hutchins, Stafford Sanne, Atresh Hasan, Mohammad M. Chen, Zhanping Kulkarni, Jaydeep P. Intel Corporation Department of Logic Technology Development AustinTX78746 United States Intel Corporation Department of Logic Technology Development HillsboroOR97124 United States The University of Texas at Austin Electrical and Computer Engineering Department AustinTX78712 United States

A fast, accurate, single-rail voltage detection circuit (VDC) is presented. Low voltage operation is achieved by a variable gain Charge Pump (CP) followed by a Low-Dropout regulator (LDO). An Open-loop Band Gap Reference (BGREF), passed to a dynamic comparator, achieves an undervoltage trip point of 0.62V with 8.7mV sigma, and an overvoltage trip point of 1.22V with 12mV sigma, demonstrated on Intel 4 silicon prototype. The design operates without any filter cap, allowing a fast, power-on ramp of 2μs, and brown-out detection of © 2018 IEEE.

关键词： Phase comparators

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A 5-V-Program 1-V-Sense Anti-Fuse technology Featuring On-Demand Sense and Integrated Power Delivery in a 22-nm Ultra Low Power FinFET Process

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IEEE Solid-State Circuits Letters 2021年 4卷 2-5页

作者： Kulkarni, Sarvesh H. Ikram, Umaira Bhatt, Kedar Chao, Yu-Lin Chang, Yao-Feng Jenkins, Ian Murari, Venkatesh Thambithurai, David Hasan, Mohammad Li, Jiabo Paulson, Leif R. Sell, Bernhard Bhattacharya, Uddalak Zhang, Ying Department of Logic Technology Development Intel Corporation HillsboroOR United States

A 11.56-kbit one-Time programmable secure array featuring Intel's first high-volume manufacturing (HVM) ready anti-fuse memory using the 22FFL process technology is reported. First, design and process technology are co-optimized to minimize the operating voltage, peripheral reliability stress, and area with dual gate-oxide 2-Transistor (2T) bit cells. Second, a best reported array density and 1-V sense endurance supported by a low-voltage dynamic scheme that meets on-demand read requirements at a yield of 99.99% are demonstrated. Third, this is the first demonstration of integrated power delivery for anti-fuse memory in FinFET technologies. With program voltage limited to 5 V, 2-stage 1.8-V charge pumps improve system area and integration. © 2018 IEEE.

关键词： FinFET

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Impact of interfacial chemistry on adhesion and electromigration in Cu interconnects

Impact of interfacial chemistry on adhesion and electromigra...

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Advanced Metallization Conference 2004, AMC 2004

作者： Zhou, Ying Scherban, Tracey Xu, Guanghai He, Jun Miner, Barbara Jan, Chia-Hong Ott, Andrew O'Loughlin, Jennifer Ingerly, Doug Leu, Jihperng Technology Development Quality and Reliability Logic Technology Development Intel Corporation Hillsboro OR 97124 Portland Technology Development Logic Technology Development Intel Corporation Hillsboro OR 97124

The impact of etch-stop (ES)/Cu interfacial chemistry on adhesion and electromigration (EM) has been systematically investigated by varying Cu surface chemistry, etch-stop film chemistry, metal capping layers, and thermal annealing conditions. Adhesion and EM improvement directly correlate with reducing interfacial oxygen for all the systems studied. While the adhesion of freshly deposited ES films strongly depends on the Cu surface chemistry and ES deposition conditions, the hermeticity of the ES film significantly impacts the film and interface chemistry during subsequent processing and thermal cycles, consequently affecting the long term stability of adhesion and electromigration performance. The mechanism for the correlation and material properties governing the interfacial chemistry will be discussed. © 2005 Materials Research Society.

关键词： Copper

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Computational electromagnetics for high-frequency IC design

Computational electromagnetics for high-frequency IC design

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IEEE Antennas and Propagation Society Symposium 2004 Digest held in Conjunction with: USNC/URSI National Radio Science Meeting

作者： Jiao, Dan Dai, Changhong Lee, Shiuh-Wuu Arabi, Tawfik R. Taylor, Greg Logic Technology Development Intel Corporation

In this talk, we will first discuss the need for computational electromagnetics (CEM) in high-frequency IC design. We will then review the recent advancements in CEM, present chip design challenges to CEM analysis, and analyze the shortcomings of current CEM methodology. We will then proceed to emphasize the importance of chip-design-driven CEM development, and finally present some promising full-wave electromagnetic-based solutions that can achieve full-chip analysis and design.

关键词： Electromagnetism

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Dummy poly removal impact factors and improvement in HKMG last process

Dummy poly removal impact factors and improvement in HKMG la...

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作者： Zeng, Yizhi Zhao, Jie Gao, Hanjie Awuti, Kurban Song, Woeiji Yu, Shaofeng Zhang, Qin Lin, Yihui Liu, Jialei Liu, H.X. Logic Technology and Development Center SMIC 201312 China

ISBN: (纸本)9781607685395

For 20/16nm HK-last and MG-last process, Dummy poly is removed by Wet process. This paper studies the factors impacting the dummy poly removal process, and presents some models to explain the impacting factors. Implant process is one of main factors influencing dummy poly removal capability because the differences of implant ions and doping amount into dummy poly induce difference of poly removal rate by wet process. We also study poly surface single clean, multiple clean and thermal process. Based on the model, we plan N-type doping poly and P-type doping poly with different ion doping amounts on blank wafer and 20nm structure wafers to evaluate dummy poly removal. We find dummy poly removal rate is different between N-type doping poly and P-type doping poly, and receive different dummy poly removal trend by ion amount on N-type doping poly and P-type doping poly. The model can help to improve dummy poly removal process control. © 2014 The Electrochemical Society.

关键词： Ions

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Intel PowerVia technology: Backside Power Delivery for High Density and High-Performance Computing

Intel PowerVia Technology: Backside Power Delivery for High ...

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2023 IEEE Symposium on VLSI technology and Circuits, VLSI technology and Circuits 2023

作者： Hafez, W. Agnihotri, P. Asoro, M. Aykol, M. Bains, B. Bambery, R. Bapna, M. Barik, A. Chatterjee, A. Chiu, P.C. Chu, T. Firby, C. Fischer, K. Fradkin, M. Greve, H. Gupta, A. Haralson, E. Haran, M. Hicks, J. Illa, A. Jang, M. Klopcic, S. Kobrinsky, M. Kuns, B. Lai, H.-H. Lanni, G. Lee, S.-H. Lindert, N. Lo, C.-L. Luo, Y. Malyavanatham, G. Marinkovic, B. Maymon, Y. Nabors, M. Neirynck, J. Packan, P. Paliwal, A. Pantisano, L. Paulson, L. Penmatsa, P. Prasad, C. Puls, C. Rahman, T. Ramaswamy, R. Samant, S. Sell, B. Sethi, K. Shah, F. Shamanna, M. Shang, K. Li, Q. Sibakoti, M. Stoeger, J. Strutt, N. Thirugnanasambandam, R. Tsai, C. Wang, X. Wang, A. Wu, S.-J. Xu, Q. Zhong, X.-H. Natarajan, S. Intel Corporation Logic Technology Development HillsboroOR United States

ISBN: (纸本)9784863488069

This paper presents a high-yielding backside power delivery (BPD) technology, PowerVia, implemented on Intel 4 finFET process. PowerVia more directly integrates power delivery to the transistor as compared to published buried power rail schemes, enabling additional wiring resources on front side for signal routing. A fabricated E-core with > 90% cell utilization showed > 30% platform voltage droop improvement and 6% frequency benefit compared to a similar design without PowerVia. Transistor performance, reliability, and fault isolation capability is detailed. © 2023 JSAP.

关键词： VLSI circuits

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