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检索条件"机构=Logic Technology Development"
共 403 条 记 录，以下是1-10 订阅
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An Intel 3 Advanced FinFET Platform technology for High Performance Computing and SOC Product Applications
An Intel 3 Advanced FinFET Platform Technology for High Perf...
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2024 IEEE Symposium on VLSI technology and Circuits, VLSI technology and Circuits 2024
作者： Hafez, W. Abanulo, D. Abdelkader, M. An, S. Auth, C. Bahr, D. Balakrishnan, V. Bambery, R. Beck, M. Bhargava, M. Bhowmick, S. Biggs-Houck, J. Birdsall, J. Caselli, D. Chang, H.-Y. Chang, Y. Chaudhuri, R. Chauhan, S. Chen, C. Chikarmane, V. Chikkadi, K. Chu, T. Connor, C. De Alba, R. Deng, Y. Destefano, C. Diana, D. Dong, Y. Elfick, P. Elko-Hansen, T. Fallahazad, B. Fang, Y. Gala, D. Garg, D. Geppert, C. Govindaraju, S. Grimm, W. Grunes, H. Guler, L. Guo, Z. Gupta, A. Hattendorf, M. Havelia, S. Hazra, J. Islam, A. Jain, A. Jaloviar, S. Jamil, M. Jang, M. Kabir, M. Kameswaran, J. Karl, E. Kelgeri, S. Kennedy, A. Kilroy, C. Kim, J. Kim, Y. Krishnan, D. Lee, G. Lee, H.-P. Li, Q. Lin, H. Luk, A. Luo, Y. MacFarlane, P. Mamun, A. Marla, K. Mayeri, D. McKenna, E. Miah, A. Mistry, K. Mleczko, M. Moon, S. Nardi, D. Natarajan, S. Nathawat, J. Nolph, C. Nugroho, C. Nyhus, P. Oni, A. Packan, P. Pak, D. Paliwal, A. Pandey, R. Paredes, I. Park, K. Paulson, L. Pierre, A. Plekhanov, P. Prasad, C. Ramaswamy, R. Riley, J. Rode, J. Russell, R. Ryu, S. Saavedra, H. Salisbury, T. Sandford, J. Shah, F. Shang, K. Shekhar, P. Shu, A. Skoug, E. Sohn, J. Song, J. Sprinkle, M. Su, J. Tan, A. Troeger, T. Tsao, R. Vaidya, A. Wallace, C. Wang, X. Wang, H. Ward, C. Wickramaratne, S. Wills, M. Wu, T. Xia-Hua, Z. Xu, S. Yashar, P. Yaung, J. Yu, Y. Zilm, M. Sell, B. Logic Technology Development Intel Corporation HillsboroOR United States
An advanced Intel 3 FinFET technology is presented that has been optimized to provide 10% logic scaling, a full node of performance improvement and improved reliability compared to Intel 4. Through transistor enhancem...
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Intel PowerVia technology: Backside Power Delivery for High Density and High-Performance Computing
Intel PowerVia Technology: Backside Power Delivery for High ...
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2023 IEEE Symposium on VLSI technology and Circuits, VLSI technology and Circuits 2023
作者： Hafez, W. Agnihotri, P. Asoro, M. Aykol, M. Bains, B. Bambery, R. Bapna, M. Barik, A. Chatterjee, A. Chiu, P.C. Chu, T. Firby, C. Fischer, K. Fradkin, M. Greve, H. Gupta, A. Haralson, E. Haran, M. Hicks, J. Illa, A. Jang, M. Klopcic, S. Kobrinsky, M. Kuns, B. Lai, H.-H. Lanni, G. Lee, S.-H. Lindert, N. Lo, C.-L. Luo, Y. Malyavanatham, G. Marinkovic, B. Maymon, Y. Nabors, M. Neirynck, J. Packan, P. Paliwal, A. Pantisano, L. Paulson, L. Penmatsa, P. Prasad, C. Puls, C. Rahman, T. Ramaswamy, R. Samant, S. Sell, B. Sethi, K. Shah, F. Shamanna, M. Shang, K. Li, Q. Sibakoti, M. Stoeger, J. Strutt, N. Thirugnanasambandam, R. Tsai, C. Wang, X. Wang, A. Wu, S.-J. Xu, Q. Zhong, X.-H. Natarajan, S. Intel Corporation Logic Technology Development HillsboroOR United States
This paper presents a high-yielding backside power delivery (BPD) technology, PowerVia, implemented on Intel 4 finFET process. PowerVia more directly integrates power delivery to the transistor as compared to publishe... 详细信息
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Direct print EUV patterning of tight pitch metal layers for Intel 18A process technology node  2
Direct print EUV patterning of tight pitch metal layers for ...
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DTCO and Computational Patterning II 2023
作者： Venkatesan, R. Guven, C. Bhawe, D. Greenwood, A.R. Zhang, Z. Gupta, P. Saksena, P. Rodriguez, R. Moumen, N. Bains, B. Sun, P. Aykol, M. Wallace, C. Bigwood, R. Fischer, K. Logic Technology Development Intel Corporation 2501 NE Century Blvd HillsboroOR97124 United States
This paper describes the direct print Extreme Ultra Violet (EUV) technology used for lithographic patterning of ~30-36 nm pitch metal layers of Intel 18A technology node. Direct print EUV delivers cost effective pitch... 详细信息
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Intel 4 CMOS technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing
Intel 4 CMOS Technology Featuring Advanced FinFET Transistor...
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2022 IEEE Symposium on VLSI technology and Circuits, VLSI technology and Circuits 2022
作者： Sell, B. An, S. Armstrong, J. Bahr, D. Bains, B. Bambery, R. Bang, K. Basu, D. Bendapudi, S. Bergstrom, D. Bhandavat, R. Bhowmick, S. Buehler, M. Caselli, D. Cekli, S. Chaganti, Vrsk. Chang, Y.J. Chikkadi, K. Chu, T. Crimmins, T. Darby, G. Ege, C. Elfick, P. Elko-Hansen, T. Fang, S. Gaddam, C. Ghoneim, M. Gomez, H. Govindaraju, S. Guo, Z. Hafez, W. Haran, M. Hattendorf, M. Hu, S. Jain, A. Jaloviar, S. Jang, M. Kameswaran, J. Kapinus, V. Kennedy, A. Klopcic, S. Krishnan, D. Leib, J. Lin, Y.-T. Lindert, N. Liu, G. Loh, O. Luo, Y. Mani, S. Mleczko, M. Mocherla, S. Packan, P. Paik, M. Paliwal, A. Pandey, R. Patankar, K. Pipes, L. Plekhanov, P. Prasad, C. Prince, M. Ramalingam, G. Ramaswamy, R. Riley, J. Perez, J. R. Sanchez Sandford, J. Sathe, A. Shah, F. Shim, H. Subramanian, S. Tandon, S. Tanniru, M. Thakurta, D. Troeger, T. Wang, X. Ward, C. Welsh, A. Wickramaratne, S. Wnuk, J. Xu, S.Q. Yashar, P. Yaung, J. Yoon, K. Young, N. Intel Corporation Logic Technology Development HillsboroOR United States
A new advanced CMOS FinFET technology, Intel 4, is introduced that extends Moore's law by offering 2X area scaling of the high performance logic library and greater than 20% performance gain at iso-power over Inte... 详细信息
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An Intel 3 Advanced FinFET Platform technology for High Performance Computing and SOC Product Applications
An Intel 3 Advanced FinFET Platform Technology for High Perf...
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Symposium on VLSI technology
作者： W. Hafez D. Abanulo M. Abdelkader S. An C. Auth D. Bahr V. Balakrishnan R. Bambery M. Beck M. Bhargava S. Bhowmick J. Biggs-houck J. Birdsall D. Caselli H.-Y. Chang Y. Chang R. Chaudhuri S. Chauhan C. Chen V. Chikarmane K. Chikkadi T. Chu C. Connor R. De Alba Y. Deng C. Destefano D. Diana Y. Dong P. Elfick T. Elko-hansen B. Fallahazad Y. Fang D. Gala D. Garg C. Geppert S. Govindaraju W. Grimm H. Grunes L. Guler Z. Guo A. Gupta M. Hattendorf S. Havelia J. Hazra A. Islam A. Jain S. Jaloviar M. Jamil M. Jang M. Kabir J. Kameswaran E. Karl S. Kelgeri A. Kennedy C. Kilroy J. Kim Y. Kim D. Krishnan G. Lee H.-P. Lee Q. Li H. Lin A. Luk Y. Luo P. Macfarlane A. Mamun K. Marla D. Mayeri E. Mckenna A. Miah K. Mistry M. Mleczko S. Moon D. Nardi S. Natarajan J. Nathawat C. Nolph C. Nugroho P. Nyhus A. Oni P. Packan D. Pak A. Paliwal R. Pandey I. Paredes K. Park L. Paulson A. Pierre P. Plekhanov C. Prasad R. Ramaswamy J. Riley J. Rode R. Russell S. Ryu H. Saavedra T. Salisbury J. Sandford F. Shah K. Shang P. Shekhar A. Shu E. Skoug J. Sohn J. Song M. Sprinkle J. Su A. Tan T. Troeger R. Tsao A. Vaidya C. Wallace X. Wang H. Wang C. Ward S. Wickramaratne M. Wills T. Wu Z. Xia-hua S. Xu P. Yashar J. Yaung Y. Yu M. Zilm B. Sell Logic Technology Development Intel Corporation Hillsboro Oregon USA
An advanced Intel 3 FinFET technology is presented that has been optimized to provide 10% logic scaling, a full node of performance improvement and improved reliability compared to Intel 4. Through transistor enhancem... 详细信息
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A 5-V-Program 1-V-Sense Anti-Fuse technology Featuring On-Demand Sense and Integrated Power Delivery in a 22-nm Ultra Low Power FinFET Process
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IEEE Solid-State Circuits Letters 2021年 4卷 2-5页
作者： Kulkarni, Sarvesh H. Ikram, Umaira Bhatt, Kedar Chao, Yu-Lin Chang, Yao-Feng Jenkins, Ian Murari, Venkatesh Thambithurai, David Hasan, Mohammad Li, Jiabo Paulson, Leif R. Sell, Bernhard Bhattacharya, Uddalak Zhang, Ying Department of Logic Technology Development Intel Corporation HillsboroOR United States
A 11.56-kbit one-Time programmable secure array featuring Intel's first high-volume manufacturing (HVM) ready anti-fuse memory using the 22FFL process technology is reported. First, design and process technology a... 详细信息
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Space development Agency burst mode on-off keyed waveform for long range intersatellite optical communications  37
Space Development Agency burst mode on-off keyed waveform fo...
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Free-Space Laser Communications XXXVII 2025
作者： Carlson, Robert Chterev, Ianko Sefler, George Rose, Todd S. Nee, Phil Klimcak, Charles Gupta, Shantanu Freeman, Wade Wayne, David Cote, Nick Kepler, Daniel Butterfield, Michael Rahimzadeh, Stephanos The Aerospace Corp United States Smart Logic United States Space Development Agency United States Modern Technology Solutions Inc. United States GoLion LLC Russia
The SDA OCT Standard v.3.1.0 defines a 2500 Mbaud NRZ on-off keyed (OOK) waveform for space-space link connectivity between SDA pLEO satellites separated by up to 5500 km. For longer range 20,000 km MEO-LEO links, the... 详细信息
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Selective Layer Transfer: Industry First Heterogeneous Integration technology Enabling Ultra-Fast Assembly & Sub-1um Chiplet Thickness for Next Generation AI & Compute Applications
Selective Layer Transfer: Industry First Heterogeneous Integ...
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2024 IEEE International Electron Devices Meeting, IEDM 2024
作者： Elsherbini, Adel Talukdar, Tushar Sounart, Thomas Nordeen, Paul Vyatskikh, Andrey Rawlings, Brandon Eid, Feras Yaghoobi, Mohammadreza Pawashe, Chytra Kloster, Grant Bedoya, Felipe Brezinski, William Vreeland, Richard Antonana, Marta Anguera Barnett, Herbert Dogiamis, Georgios Yu, Qiang Liff, Shawna Swan, Johanna Intel Foundry Technology Research ChandlerAZ United States Logic Technology Development ChandlerAZ United States Design Enablement ChandlerAZ United States Design Enablement HillsboroOR United States
We present a novel heterogeneous integration technology, selective layer transfer (SLT), which enables ultra-fast (>100X faster than traditional assembly), cost efficient hybrid or fusion bonding of specific chiple... 详细信息
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Assessing Impact of Non-Uniform Localized Heating on Reliability
Assessing Impact of Non-Uniform Localized Heating on Reliabi...
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IEEE International Conference on Interconnect technology
作者： Yoon Jo Kim Edwin B. Ramayya Lei Jiang Jason Jopling Rahim Kasim Logic Technology Development Quality and Reliability Intel Corporation Hillsboro Oregon U.S.A Logic Technology Development Intel Corporation Hillsboro Oregon U.S.A
Moore’s Law-driven technology improvements have led to a significant increase in power density across a multitude of market segments, from mobile to HEDT (high-end desktop) and servers. This, in turn, has led to an i... 详细信息
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Selective Layer Transfer: Industry First Heterogeneous Integration technology Enabling Ultra-Fast Assembly & Sub-1um Chiplet Thickness for Next Generation AI & Compute Applications
Selective Layer Transfer: Industry First Heterogeneous Integ...
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International Electron Devices Meeting (IEDM)
作者： Adel Elsherbini Tushar Talukdar Thomas Sounart Paul Nordeen Andrey Vyatskikh Brandon Rawlings Feras Eid Mohammadreza Yaghoobi Chytra Pawashe Grant Kloster Felipe Bedoya William Brezinski Richard Vreeland Marta Anguera Antonana Herbert Barnett Georgios Dogiamis Qiang Yu Shawna Liff Johanna Swan Intel Foundry Technology Research Logic Technology Development Design Enablement Chandler AZ Design Enablement Hillsboro OR
We present a novel heterogeneous integration technology, selective layer transfer (SLT), which enables ultra-fast (>100X faster than traditional assembly), cost efficient hybrid or fusion bonding of specific chiple... 详细信息
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