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International Electron Devices Meeting (IEDM)

作者： D. B. Ingerly S. Amin L. Aryasomayajula A. Balankutty D. Borst A. Chandra K. Cheemalapati C. S. Cook R. Criss K. Enamul W. Gomes D. Jones K. C. Kolluru A. Kandas G.-S. Kim H. Ma D. Pantuso C.F. Petersburg M. Phen-givoni A. M. Pillai A. Sairam P. Shekhar P. Sinha P. Stover A. Telang Z. Zell Logic Technology Development Intel Corporation Hillsboro OR

This paper presents the key silicon features of Intel's 3D stacking technology, Foveros, as it is used to enable logic-on-logic die stacking. A robust face-to-face die connection is enabled with a high yielding, robust microbump connection. Additionally, we describe the low resistance TSVs used for connection to the package along with their electrical properties.

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A new technique for the characterization of the adhesion in integrated circuit interconnect structures

A new technique for the characterization of the adhesion in ...

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2005 Materials Research Society Spring Meeting

作者： Ocana, Ibon Molina, Jon M. Gonzalez, Diego Elizalde, M. Reyes Sanchez, Jose M. Martinez-Esnaola, Jose M. Gil-Sevillano, Javier Scherban, Tracey Pantuso, Daniel Sun, Brad Xu, Guanghai Miner, Barbara He, Jun Maiz, Jose A. P. Manuel Lardizabal 15 20018 San Sebastián Spain Logic Technology Development Intel Corporation Hillsboro OR 97124 United States

A new testing technique for the characterization of the mechanical behavior of the interconnect structures of integrated circuit devices is introduced in this paper. Modified cross-sectional nanoindentation (MCSN) is the result of extending cross-sectional indentation (CSN) to patterned structures. As in conventional CSN, a Berkovich indenter is used to initiate fracture in the silicon substrate beneath the interconnect structure. The cracks propagate through this structure, preferentially along the weakest interfaces in the system. A FIB (Focused Ion Beam) is used for sample preparation, machining a trench parallel to the indentation surface. In this way, the crack growth can be better controlled and the problem may be modeled in two dimensions. The technique has been used to study crack propagation in patterned structures as a function of thin film composition and processing. The results obtained, in terms of crack length along each interface studied, correlate well with the fracture energy measured by four-point bending (4 PB) in blanket films of the same materials. Finite element modeling of the stress fields in the vicinity of the crack tip has been carried out to understand the crack paths observed. © 2005 Materials Research Society.

关键词： Integrated circuits

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Node sensitivity analysis for soft errors in CMOS logic

Node sensitivity analysis for soft errors in CMOS logic

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IEEE International Test Conference, ITC 2005

作者： Gill, Balkaran S. Papachristou, Chris Wolff, Francis G. Seifert, Norbert Department of Electrical Engineering and Computer Science Case Western Reserve University Cleveland OH Logic Technology Development Q and R Intel Corporation Hillsboro OR

ISBN: (纸本)0780390393

In this paper, we introduce an approach for computing soft error susceptibility of nodes in large CMOS circuits at the transistor level. The node sensitivity depends on the electrical, logic, and timing masking. An efficient technique is developed to compute the electrical masking of nodes using characterization tables and inverse pulse propagation. We generated these tables for every logic cell of the library using Spice simulations for a 100nm process technology. An additional technique to compute the logic masking of the transistor nodes using an automatic test pattern generation tool is described. Our results show that our approach has Spice like accuracy but it is several orders of magnitude faster than Spice. This approach can be used to analyze the vulnerability of circuits to single event upsets at the chip level. Results are provided for ISCAS85 benchmark circuits. © 2005 IEEE.

关键词： CMOS integrated circuits

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High-/spl kappa//metal-gate stack and its MOSFET characteristics

IEEE Electron Device Letters

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IEEE Electron Device Letters 2004年第6期25卷 408-410页

作者： R. Chau S. Datta M. Doczy B. Doyle J. Kavalieros M. Metz Components Research Logic Technology Development Intel Corporation Hillsboro OR USA

We show experimental evidence of surface phonon scattering in the high-/spl kappa/ dielectric being the primary cause of channel electron mobility degradation. Next, we show that midgap TiN metal-gate electrode is effective in screening phonon scattering in the high-/spl kappa/ dielectric from coupling to the channel under inversion conditions, resulting in improved channel electron mobility. We then show that other metal-gate electrodes, such as the ones with n+ and p+ work functions, are also effective in improving channel mobilities to close to those of the conventional SiO/sub 2//poly-Si stack. Finally, we demonstrate this mobility degradation recovery translates directly into high drive performance on high-/spl kappa//metal-gate CMOS transistors with desirable threshold voltages.

关键词： MOSFET circuits Dielectrics Electrodes Hafnium oxide Phonons Electron mobility Degradation Tin Threshold voltage Optical scattering

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Study of fin CD controllability for FinFET manufacturing

Study of fin CD controllability for FinFET manufacturing

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China Semiconductor technology International Conference (CSTIC)

作者： Hai Zhao Gang Mao Rex Yang Technology Research and Development SMIC Logic Technology and Development Center SMIC Shanghai China

In this paper, several steps which would affect CD variation or Fin CD loss were analyzed during FinFET manufacturing, and then we figured out the dominant ones causing CD loss. Finally, an optimization guideline for Fin CD control in process integration was suggested for better Fin CD controllability. It's not only good for Fin CD control, but also good for wide process margin to integrate smaller Fin CD beyond 20nm technology node.

关键词： logic gates Performance evaluation FinFETs Industries Mass production Surface treatment Annealing

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Challenges and opportunities for circuit design in nano-scale CMOS technologies

Challenges and opportunities for circuit design in nano-scal...

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European Conference on Solid-State Circuits (ESSCIRC)

作者： Kevin Zhang Logic Technology Development Intel Corporation Hillsboro OR USA

CMOS technology scaling trend and latest technology innovations will be discussed first. Then the paper will focus on the challenges in several critical circuit areas, including both analog and memory for high-perform... 详细信息

关键词： Phase locked loops CMOS integrated circuits CMOS technology Transistors Technological innovation Program processors Analog circuits

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A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors

A 45nm low power system-on-chip technology with dual gate (l...

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International Electron Devices Meeting (IEDM)

作者： C.-H. Jan P. Bai S. Biswas M. Buehler Z.-P. Chen G. Curello S. Gannavaram W. Hafez J. He J. Hicks U. Jalan N. Lazo J. Lin N. Lindert C. Litteken M. Jones M. Kang K. Komeyli A. Mezhiba S. Naskar S. Olson J. Park R. Parker L. Pei I. Post N. Pradhan C. Prasad M. Prince J. Rizk G. Sacks H. Tashiro D. Towner C. Tsai Y. Wang L. Yang J.-Y. Yeh J. Yip K. Mistry Logic Technology Development Intel Corporation Hillsboro OR USA

A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products. PMOS/NMOS logic transistor drive currents of 0.86/1.08 mA/um, respectively, have been achieved at 1.1 V and off-state leakage of 1 nA/um. Record RF performance for a mainstream 45 nm bulk CMOS technology has been achieved with measured f T /f MAX values of 395 GHz/410 GHz for NMOS and 300 GHz/325 GHz for PMOS with 28 nm L gate transistors. HV I/O transistors with robust reliability and other SOC features, including linear resistors, MIS and MIM capacitors, varactors, inductors, vertical BJTs, precision diodes and high density OTP fuses are employed for HV I/O, analog and RF circuit integration.

关键词： Power systems logic gates High K dielectric materials High-K gate dielectrics Silicon CMOS technology CMOS logic circuits MOS devices Radio frequency System-on-a-chip

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Reducing Variation in Advanced logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS

Reducing Variation in Advanced Logic Technologies: Approache...

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International Electron Devices Meeting (IEDM)

作者： Kelin J. Kuhn Logic Technology Development Intel Corporation Hillsboro OR USA

This paper presents an overview of process variation effects, including examples of mitigation strategies and test methods. Experimental and theoretical comparisons are presented for 45 nm and 65 nm RDF. SRAM matching and interconnect variation is discussed for both 65 nm and 45 nm, including examples of process and design mitigation strategies. Use of ring oscillators for detailed measurement of within-wafer and within-die variation is illustrated for 65 nm and 45 nm products.

关键词： CMOS logic circuits logic design CMOS technology Process design Manufacturing processes CMOS process Testing Resource description framework Random access memory Ring oscillators

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45nm High-k + Metal Gate Strain-Enhanced CMOS Transistors

45nm High-k + Metal Gate Strain-Enhanced CMOS Transistors

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2008 IEEE Custom Integrated Circuits Conference (CICC 2008), vol.2

作者： Chris Auth Logic Technology Development Intel Corporation Hillsboro OR USA

At the 45nm technology node, high-k + metal gate transistors were introduced for the first time on a high-volume manufacturing process [1]. The introduction of a high-k gate dielectric enabled transistors with a 0.7×reduction in Tox (electrical gate oxide thickness) while reducing gate leakage 1000× for the PMOS and 25× for the NMOS transistors. Dual-band edge workfunction metal gates were introduced, eliminating polysilicon gate depletion and providing compatibility with the high-k gate dielectric. High-k + Metal gates have also been shown to have improved variability at the 45nm node [2]. In addition to the high-k + metal gate, the 35nm gate length CMOS transistors have been integrated with a third generation of strained silicon and have demonstrated the highest drive currents to date for both NMOS and PMOS. An SRAM cell size of 0.346μm{sup}2 has been achieved while using 193nm dry lithography. High yield and reliability has been demonstrated on multiple single, dual-, quad- and six-core microprocessors.

关键词： High K dielectric materials High-K gate dielectrics CMOS technology Manufacturing processes Gate leakage MOSFETs Dual band Silicon MOS devices Random access memory

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Moore's Law Past 32nm: Future Challenges in Device Scaling

Moore's Law Past 32nm: Future Challenges in Device Scaling

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International Workshop on Computational Electronics

作者： Kelin J. Kuhn Logic Technology Development Intel Corporation Hillsboro OR USA

ISBN: (纸本)9781424439256

This paper explores the challenges facing process generations past the 32 nm technology node and speculates on what new solutions will be needed. The challenges facing planar and multiple-gate devices are compared and contrasted. Resistance and capacitance challenges are reviewed in relation to past history and on-going research. Key enhancers such as high-k metal-gate (HiK-MG), substrate and channel orientation, as well as NMOS and PMOS stress are discussed in relation to the challenges of the coming transistor generations.

关键词： Moore's Law Transistors Capacitive sensors Capacitance Stress Degradation MOS devices Doping Electrostatic discharge History

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