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Decoupling of Ion Diffusivity and Electromobility in Porous Dielectrics

ECS Meeting Abstracts 2016年第16期MA2016-01卷

作者： Ye Fan Rizwan Ali Sean W. King Jeff Bielefeld Marius K Orlowski Virginia Tech ECE Department Virginia Tech Intel Corporation Intel Inc Logic Technology Development Lab ECE Department Virginia Tech

In an effort to lower the interconnect time delay and address the latency problem, porous low-k dielectrics are being currently explored as a low-k BEOL dielectric. Because of low density, porous dielectrics suffer from excessive impurity diffusion and from ion electromigration when the interconnect lines are powered. This paper investigates the relation of ion diffusivity and electro-mobility in porous dielectrics. Metal-Insulator-Metal (MIM) structures have been manufactured with bottom Cu electrode and with top island-shaped W or Pt counter-electrode. The porous dielectric was a-SiC:H or a-SiOC:H with level of porosity varying between 8% to 25%. The thickness of the porous dielectric is 20 nm and the dielectric constant k varied between 3.1 (@ 8% porosity) and 2.5 (@25% porosity). Some devices have a 2 nm SiCN diffusion barrier (DB), either at the Cu or W/Pt electrode or at both electrodes. The SiCN layers serve a dual-purpose: i) to prevent Cu diffusion, and ii) to prevent Cu, W, and Pt protrusion into pores and cavities of porous dielectrics. A bulk majority of devices have been found intrinsically conductive, i.e. conductive from the beginning and less than 10% - only those with at least one DB - displayed resistive switching (RS) behavior. Of those devices that showed resistive switching behavior, devices with higher porosity showed consistently higher forming voltage Vform of Cu filaments than dielectrics with lower porosity. This is strange in view of the fact that most of the devices even of high porosity where intrinsically conductive indicating a very high degree of Cu diffusion. For a-SiC:H film with 8% porosity we find Vform ≈ 0V, compared with Vform= 0.4 - 0.5V for 12% porosity and Vform= 1.4 V- 2.3 V for 25% porosity. Why should electromigration require higher electric field when the Cu diffusivity appears to be equally strong? In nonporous materials the diffusivity D and mobility m of charged particles such as an ion is related by the Einstein relat

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High sigma measurement of random threshold voltage variation in 14nm logic FinFET technology

High sigma measurement of random threshold voltage variation...

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Symposium on VLSI technology

作者： M. D. Giles N. Arkali Radhakrishna D. Becher A. Kornfeld K. Maurice S. Mudanai S. Natarajan P. Newman P. Packan T. Rakshit Design Technology Solutions Intel Corporation Hillsboro OR USA Logic Technology Development Intel Corporation Hillsboro OR USA Device Development Group Intel Corporation Hillsboro OR USA

Random variation of threshold voltage (Vt) in MOSFETs plays a central role in determining the minimum operating voltage of products in a given process technology. Properly characterizing Vt variation requires a large volume of measurements of minimum size devices to understand the high sigma behavior. At the same time, a rapid measurement approach is required to keep the total measurement time practical. Here we describe a new test structure and measurement approach that enables practical characterization of Vt distributions to high sigma and its application to 14nm logic FinFET technology. We show that both NMOS and PMOS single fin devices have very low random Vt variation of 19mV and 24mV respectively, normally distributed out to +/-5σ.

关键词： Threshold voltage FinFETs logic gates Time measurement Periodic structures

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Decoupling of Ion Diffusivity and Electromobility in Porous Dielectrics

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ECS Transactions 2016年第2期72卷

Porous back-end dielectric materials with porosity from 8% to 25%, sandwiched between Cu and W/Pt electrodes, have been investigated in terms of Cu diffusivity and mobility. In nonporous materials the diffusivity D and mobility m of charged particles such as an ion is related by the Einstein relation: μ=D q/kT. Here, we present evidence that in porous materials the diffusivity and mobility are decoupled on a global scale, even though the Einstein relation still holds locally. In porous materials, the voids lying in the path of the ion present an impenetrable barrier for ion migration. Voids can be only overcome by a detour around the obstacle by virtue of diffusion. We propose a modified relation between diffusivity and mobility in porous materials by μ=fpD q/kT where a porosity-tortuosity factor fp <1 is introduced. The factor fp depends on porosity and tortuosity of the porous material.

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Atomic layer deposited hybrid organic-inorganic aluminates as potential low-κ dielectric materials

Atomic layer deposited hybrid organic-inorganic aluminates a...

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2015 MRS Spring Meeting

作者： Klepper, Karina B. Miikkulainen, Ville Nilsen, Ola Fjellvag, Helmer Liu, Ming Dutta, Dhanadeep Gidley, David Lanford, William Ross, Liza Li, Han King, Sean W. Department of Chemistry Center for Materials Science and Nanotechnology University of Oslo Oslo Norway Department of Physics University of Michigan Ann ArborMI United States Department of Physics University of Albany AlbanyNY United States Logic Technology Development Intel Corporation HillsboroOR United States

ISBN: (纸本)9781510826458

The material properties of atomic layer deposited hybrid organic-inorganic aluminate thin films have been evaluated for potential low dielectric constant (i.e. low-κ) applications. The hybrid aluminates were deposited using trimethyl aluminum and various linear and aromatic carboxylic acids. The observed electrical and mechanical properties for the hybrid aluminate films varied greatly depending on the selected organic acid with values ranging from 2.5 to 5.1 and Young's modulus ranging from 6 to 40 GPa. Leakage currents as low as 4 x 10-10 A/cm2 (at 2 MV/cm) were obtained for films grown using saturated linear carboxylic acids. These results suggest the potential of ALD hybrid aluminate thin films for low-κ dielectric applications. © 2015 Materials Research Society.

关键词： Thin films

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Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process

Low-voltage metal-fuse technology featuring a 1.6V-programma...

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Symposium on VLSI Circuits

作者： S H Kulkarni Z Chen B Srinivasan B Pedersen U Bhattacharya K Zhang Advanced Design Logic Technology Development Intel Corporation Hillsboro OR USA NVM Solutions Group Custom Foundry Intel Corporation Hillsboro OR USA

This work introduces the first high-volume manufacturable metal-fuse technology in a 22nm tri-gate high-k metal-gate CMOS process. A high-density array featuring a 16.4μm 2 1T1R bit cell is presented that delivers a record low program voltage of 1.6V. This low-voltage operability allows the array to be coupled with logic-voltage power delivery circuits. A charge pump voltage doubler operating on a 1V voltage rail is demonstrated in this paper with healthy fusing yield.

关键词： Fuses Arrays Charge pumps Programming Microprocessors System-on-chip

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Dummy poly removal impact factors and improvement in HKMG last process

Dummy poly removal impact factors and improvement in HKMG la...

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作者： Zeng, Yizhi Zhao, Jie Gao, Hanjie Awuti, Kurban Song, Woeiji Yu, Shaofeng Zhang, Qin Lin, Yihui Liu, Jialei Liu, H.X. Logic Technology and Development Center SMIC 201312 China

ISBN: (纸本)9781607685395

For 20/16nm HK-last and MG-last process, Dummy poly is removed by Wet process. This paper studies the factors impacting the dummy poly removal process, and presents some models to explain the impacting factors. Implant process is one of main factors influencing dummy poly removal capability because the differences of implant ions and doping amount into dummy poly induce difference of poly removal rate by wet process. We also study poly surface single clean, multiple clean and thermal process. Based on the model, we plan N-type doping poly and P-type doping poly with different ion doping amounts on blank wafer and 20nm structure wafers to evaluate dummy poly removal. We find dummy poly removal rate is different between N-type doping poly and P-type doping poly, and receive different dummy poly removal trend by ion amount on N-type doping poly and P-type doping poly. The model can help to improve dummy poly removal process control. © 2014 The Electrochemical Society.

关键词： Ions

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Wafer-level electromigration for reliability monitoring: Quick-turn electromigration stress with correlation to package-level stress

Wafer-level electromigration for reliability monitoring: Qui...

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IEEE International Reliability Physics Symposium, IRPS 2015

作者： Slottke, D. Kamaladasa, R.J. Harmes, M. Tsamaret, I. Kobrinsky, M. McMullen, Timothy Dunklee, John Logic Technology Development QandR Intel Corporation HillsboroOR United States Components Research Intel Corporation HillsboroOR United States Reliability Test Products Cascade Microtech Incorporated BeavertonOR United States Applications Engineering Celadon Systems Incorporated N. St. PaulMN United States

ISBN: (纸本)9781467373623

Rapid, accurate and flexible reliability characterization capabilities are important tools in process development and monitoring. Electromigration evaluation has largely relied on packaged test structures given the need for high temperatures to provide sufficient acceleration. However, several Wafer-Level (WL) electromigration (EM) techniques and their correlation to Package-Level (PL) tests have been reported (e.g. SWEAT[1], [2], isothermal[3], tests). Presented in the this paper is a wafer-level electromigration test that addresses the PL correlation issues presented by quick-turn tests, but maintains the advantages of wafer-level and allows quick comparison to PL baseline with a significant advantage in time-to-data over PL-EM testing. Statistical matching of initial resistance (R0) and Time-to-Failure (TTF) between PL vs. WL electromigration tests on two concurrently stressed structures across sixteen reticle locations is demonstrated. This WL-EM stress technique provides equivalent TTF, with no reliance on extrapolations, whilst yielding an advantage in time-to-data relative to standard PL-EM tests. © 2015 IEEE.

关键词： Electromigration

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Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process

Low-voltage metal-fuse technology featuring a 1.6V-programma...

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Symposium on VLSI technology

作者： S H Kulkarni Z Chen B Srinivasan B Pedersen U Bhattacharya K Zhang Advanced Design Logic Technology Development Intel Corporation Hillsboro OR USA NVM Solutions Group Intel Corporation Hillsboro OR USA Custom Foundry Intel Corporation Hillsboro OR USA

关键词： Fuses Arrays Charge pumps Programming Microprocessors System-on-chip

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Interfacial layer development for 20nm high-k last integration scheme

Interfacial layer development for 20nm high-k last integrati...

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作者： Gao, Hanjie Zhao, Jie Min, Jiahua Zeng, Yizhi Awut, Kurban Song, Woeiji Yu, Shaofeng School of Materials Science and Engineering Shanghai University China Logic Technology and Development Center SMIC China

ISBN: (纸本)9781607685395

With the characteristic dimension scaling down of CMOS device, the gate leakage increases significantly and the device gets low reliability performance. Then EOT (Equivalent Oxide Thickness) should be decreased, and more performance would be gained with leakage and reliability sacrifice by an optimized dielectric interfacial layer and high-k material. In this paper, the methods to form IL are the key point of EOT scaling down with gate leakage sacrifice and post replacement metal gate (RMG) treatment lead to work function improvement with hysteresis reduction beyond 20nm node of CMOS devices. Based on data analysis we want to get some optimized conditions to make this layer an enhancement in the research of HKMG logic product process development. © 2014 The Electrochemical Society.

关键词： CMOS integrated circuits

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Stacking faults and stress memorization technique study for n-type MOSFET performance improvement in all last High-k Metal Gate process development

Stacking faults and stress memorization technique study for ...

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作者： Li, Yong Sun, Hao Ju, Jianhua Logic Technology and Development Center SMIC 201203 China School of Materials Science and Eng Shanghai University 200072 China

ISBN: (纸本)9781607685395

In this paper, the stacking faults, stress memorization technique (SMT) and their impacts on n-type MOSFET device performance were studied. SMT combines source/drain deep PAI improves short channel device electron mobility 25%, Ion/Ioff curve 8% and long channel device 10% and 4%, respectively. A mechanism why SMT improves device performance in all last HKMG (High-k Metal Gate) process was proposed. During SMT anneal, poly expands much more than the hard nitride cap, the thermal stress gain from poly transformation from an elastic state to a plastic state was transferred into the channel, the stress was then memorized by the source/drain stacking faults, that were formed during the SMT anneal at deep pre-amorphous source/drain area. After poly removal, the tensile stress still exists, as it was retained by the stacking faults. The stress intensity along channel, Sxx, is the key parameter to index the stress effect on device performance improvement;it is related to poly volume and gate length. And based on this, the reasons that long channel and short channel devices performance gain are much smaller than that of the middle channel devices were also discussed. © 2014 The Electrochemical Society.

关键词： Stacking faults

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