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检索条件"机构=Logic Technology Development"
403 条 记 录,以下是91-100 订阅
排序:
Decoupling of Ion Diffusivity and Electromobility in Porous Dielectrics
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ECS Meeting Abstracts 2016年 第16期MA2016-01卷
作者: Ye Fan Rizwan Ali Sean W. King Jeff Bielefeld Marius K Orlowski Virginia Tech ECE Department Virginia Tech Intel Corporation Intel Inc Logic Technology Development Lab ECE Department Virginia Tech
In an effort to lower the interconnect time delay and address the latency problem, porous low-k dielectrics are being currently explored as a low-k BEOL dielectric. Because of low density, porous dielectrics suffer fr...
来源: 评论
High sigma measurement of random threshold voltage variation in 14nm logic FinFET technology
High sigma measurement of random threshold voltage variation...
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Symposium on VLSI technology
作者: M. D. Giles N. Arkali Radhakrishna D. Becher A. Kornfeld K. Maurice S. Mudanai S. Natarajan P. Newman P. Packan T. Rakshit Design Technology Solutions Intel Corporation Hillsboro OR USA Logic Technology Development Intel Corporation Hillsboro OR USA Device Development Group Intel Corporation Hillsboro OR USA
Random variation of threshold voltage (Vt) in MOSFETs plays a central role in determining the minimum operating voltage of products in a given process technology. Properly characterizing Vt variation requires a large ... 详细信息
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Decoupling of Ion Diffusivity and Electromobility in Porous Dielectrics
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ECS Transactions 2016年 第2期72卷
作者: Ye Fan Rizwan Ali Sean W. King Jeff Bielefeld Marius K Orlowski Virginia Tech ECE Department Virginia Tech Intel Corporation Intel Inc Logic Technology Development Lab ECE Department Virginia Tech
Porous back-end dielectric materials with porosity from 8% to 25%, sandwiched between Cu and W/Pt electrodes, have been investigated in terms of Cu diffusivity and mobility. In nonporous materials the diffusivity D an...
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Atomic layer deposited hybrid organic-inorganic aluminates as potential low-κ dielectric materials
Atomic layer deposited hybrid organic-inorganic aluminates a...
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2015 MRS Spring Meeting
作者: Klepper, Karina B. Miikkulainen, Ville Nilsen, Ola Fjellvag, Helmer Liu, Ming Dutta, Dhanadeep Gidley, David Lanford, William Ross, Liza Li, Han King, Sean W. Department of Chemistry Center for Materials Science and Nanotechnology University of Oslo Oslo Norway Department of Physics University of Michigan Ann ArborMI United States Department of Physics University of Albany AlbanyNY United States Logic Technology Development Intel Corporation HillsboroOR United States
The material properties of atomic layer deposited hybrid organic-inorganic aluminate thin films have been evaluated for potential low dielectric constant (i.e. low-κ) applications. The hybrid aluminates were deposite... 详细信息
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Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process
Low-voltage metal-fuse technology featuring a 1.6V-programma...
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Symposium on VLSI Circuits
作者: S H Kulkarni Z Chen B Srinivasan B Pedersen U Bhattacharya K Zhang Advanced Design Logic Technology Development Intel Corporation Hillsboro OR USA NVM Solutions Group Custom Foundry Intel Corporation Hillsboro OR USA
This work introduces the first high-volume manufacturable metal-fuse technology in a 22nm tri-gate high-k metal-gate CMOS process. A high-density array featuring a 16.4μm 2 1T1R bit cell is presented that delivers a... 详细信息
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Dummy poly removal impact factors and improvement in HKMG last process
Dummy poly removal impact factors and improvement in HKMG la...
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作者: Zeng, Yizhi Zhao, Jie Gao, Hanjie Awuti, Kurban Song, Woeiji Yu, Shaofeng Zhang, Qin Lin, Yihui Liu, Jialei Liu, H.X. Logic Technology and Development Center SMIC 201312 China
For 20/16nm HK-last and MG-last process, Dummy poly is removed by Wet process. This paper studies the factors impacting the dummy poly removal process, and presents some models to explain the impacting factors. Implan... 详细信息
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Wafer-level electromigration for reliability monitoring: Quick-turn electromigration stress with correlation to package-level stress
Wafer-level electromigration for reliability monitoring: Qui...
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IEEE International Reliability Physics Symposium, IRPS 2015
作者: Slottke, D. Kamaladasa, R.J. Harmes, M. Tsamaret, I. Kobrinsky, M. McMullen, Timothy Dunklee, John Logic Technology Development QandR Intel Corporation HillsboroOR United States Components Research Intel Corporation HillsboroOR United States Reliability Test Products Cascade Microtech Incorporated BeavertonOR United States Applications Engineering Celadon Systems Incorporated N. St. PaulMN United States
Rapid, accurate and flexible reliability characterization capabilities are important tools in process development and monitoring. Electromigration evaluation has largely relied on packaged test structures given the ne... 详细信息
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Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process
Low-voltage metal-fuse technology featuring a 1.6V-programma...
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Symposium on VLSI technology
作者: S H Kulkarni Z Chen B Srinivasan B Pedersen U Bhattacharya K Zhang Advanced Design Logic Technology Development Intel Corporation Hillsboro OR USA NVM Solutions Group Intel Corporation Hillsboro OR USA Custom Foundry Intel Corporation Hillsboro OR USA
This work introduces the first high-volume manufacturable metal-fuse technology in a 22nm tri-gate high-k metal-gate CMOS process. A high-density array featuring a 16.4μm 2 1T1R bit cell is presented that delivers a... 详细信息
来源: 评论
Interfacial layer development for 20nm high-k last integration scheme
Interfacial layer development for 20nm high-k last integrati...
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作者: Gao, Hanjie Zhao, Jie Min, Jiahua Zeng, Yizhi Awut, Kurban Song, Woeiji Yu, Shaofeng School of Materials Science and Engineering Shanghai University China Logic Technology and Development Center SMIC China
With the characteristic dimension scaling down of CMOS device, the gate leakage increases significantly and the device gets low reliability performance. Then EOT (Equivalent Oxide Thickness) should be decreased, and m... 详细信息
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Stacking faults and stress memorization technique study for n-type MOSFET performance improvement in all last High-k Metal Gate process development
Stacking faults and stress memorization technique study for ...
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作者: Li, Yong Sun, Hao Ju, Jianhua Logic Technology and Development Center SMIC 201203 China School of Materials Science and Eng Shanghai University 200072 China
In this paper, the stacking faults, stress memorization technique (SMT) and their impacts on n-type MOSFET device performance were studied. SMT combines source/drain deep PAI improves short channel device electron mob... 详细信息
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