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Atomic Layer Deposited Hybrid Organic-Inorganic Aluminates as Potential Low-k Dielectric Materials

MRS Online Proceedings Library (OPL) 2015年第1期1791卷 15-20页

作者： Karina B. Klepper Ville Miikkulainen Ola Nilsen Helmer Fjellvåg Ming Liu Dhanadeep Dutta David Gidley William Lanford Liza Ross Han Li Department of Chemistry Center for Materials Science and Nanotechnology University of Oslo Oslo Norway Department of Physics University of Michigan Ann Arbor MI U.S.A. Department of Physics University of Albany Albany NY U.S.A. Logic Technology Development Intel Corporation Hillsboro OR U.S.A.

The material properties of atomic layer deposited hybrid organic-inorganic aluminate thin films have been evaluated for potential low dielectric constant (i.e. low-k) applications. The hybrid aluminates were deposited using trimethyl aluminum and various linear and aromatic carboxylic acids. The observed electrical and mechanical properties for the hybrid aluminate films varied greatly depending on the selected organic acid with k values ranging from 2.5 to 5.1 and Young’s modulus ranging from 6 to 40 GPa. Leakage currents as low as 4 x 10-10 A/cm2 (at 2 MV/cm) were obtained for films grown using saturated linear carboxylic acids. These results suggest the potential of ALD hybrid aluminate thin films for low-k dielectric applications.

关键词： atomic layer deposition dielectric elastic properties

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2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology

2nd generation embedded DRAM with 4X lower self refresh powe...

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28th IEEE Symposium on VLSI Circuits, VLSIC 2014

作者： Meterelliyoz, Mesut Al-Amoody, Fuad H. Arslan, Umut Hamzaoglu, Fatih Hood, Luke Lal, Manoj Miller, Jeffrey L. Ramasundar, Anand Soltman, Dan Wan, Ifar Wang, Yih Zhang, Kevin Logic Technology Development Intel Corporation Hillsboro OR United States Platform Engineering Group Intel Corporation Hillsboro OR United States

ISBN: (纸本)9781479933273

2nd generation 1Gbit 2GHz Embedded DRAM (eDRAM) with 4X lower self refresh power compared to prior generation is developed in 22nm Tri-Gate CMOS technology. Retention time has been improved by 3X (300us@95°C) by process and design optimizations. Source synchronous clocking is integrated in the design to reduce clock power without penalizing bandwidth. Charge pump power is reduced by 4X by employing comparator based regulation. Temperature controlled refresh enables minimum refresh power at all temperature conditions. © 2014 IEEE.

关键词： Clocks

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NMOS source-drain extension ion implantation into heated substrates

NMOS source-drain extension ion implantation into heated sub...

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International Conference on Ion Implantation technology (IIT)

作者： Leonard C. Pipes Lisa McGill Anant Jahagirdar Logic Technology Development Intel Corporation Hillsboro OR USA

The emergence of three-dimensional structures (Tri-gate, FinFET, etc.) in modern CMOS manufacturing have required new technologies to mitigate ion implant damage effects. Traditional beamline ion implant provides a well understood and well controlled approach to fin doping given that the pitches between source/drain fins and/or the polysilicon gates allow it without shadowing of active device structures. However, traditional beamline ion implant also causes silicon damage that can prove particularly problematic at the dimensions associated with modern 3-dimensional transistors. In this work we perform traditional beamline ion implants into silicon wafer substrates that are heated to elevated temperatures in an effort to mitigate ion implant damage effects. The net impact of damage mitigation using this technology is shown on flat wafers, topographical wafers, and finally on 22 nm NMOS trigate devices.

关键词： Implants Silicon Substrates Annealing Transistors Ion implantation Heating

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Integration of a 3-D capacitor into a logic interconnect stack for high performance embedded DRAM SoC technology

Integration of a 3-D capacitor into a logic interconnect sta...

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IEEE International Conference on Interconnect technology

作者： R. Brain N. Bisnik H.-P. Chen J. Neulinger N. Lindert J. Peach L. Rockford Y. Wang K. Zhang Logic Technology Development Intel Corporation Hillsboro Oregon USA

关键词： Transistors Capacitors Arrays logic gates Integrated circuit interconnections Capacitance

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A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size

A 14nm logic technology featuring 2nd-generation FinFET, air...

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International Electron Devices Meeting (IEDM)

作者： S. Natarajan M. Agostinelli S. Akbar M. Bost A. Bowonder V. Chikarmane S. Chouksey A. Dasgupta K. Fischer Q. Fu T. Ghani M. Giles S. Govindaraju R. Grover W. Han D. Hanken E. Haralson M. Haran M. Heckscher R. Heussner P. Jain R. James R. Jhaveri I. Jin H. Kam E. Karl C. Kenyon M. Liu Y. Luo R. Mehandru S. Morarka L. Neiberg P. Packan A. Paliwal C. Parker P. Patel R. Patel C. Pelto L. Pipes P. Plekhanov M. Prince S. Rajamani J. Sandford B. Sell S. Sivakumar P. Smith B. Song K. Tone T. Troeger J. Wiedemer M. Yang K. Zhang Logic Technology Development Quality and Reliability Engineering DTS Intel Corporation

A 14nm logic technology using 2 nd -generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4 th generation high-k metal gate, and 6 th -generation strained silicon, resulting in the highest drive currents yet reported for 14nm technology. This technology is in high-volume manufacturing.

关键词： Doping logic gates Market research FinFETs Random access memory

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Advanced CMOS reliability challenges

Advanced CMOS reliability challenges

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International Symposium on VLSI technology, Systems and Applications

作者： Chetan Prasad Logic Technology Development Quality and Reliability Intel Corporation Hillsboro U.S.A

This work reviews transistors of advanced CMOS process nodes from a reliability perspective and covers some of the important challenges and solutions. Physical mechanisms for various modes are investigated for 65nm to 22nm nodes with focus on disruptive changes such as HK/MG and Tri-gate/FinFET. The importance of modeling non-idealities and variation is also emphasized, and projections are made for scaling to sub-20nm with comparisons to existing research.

关键词： Degradation Optimization logic gates Integrated circuit reliability FinFETs Aging

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BTI Recovery in 22nm Tri-gate technology

BTI Recovery in 22nm Tri-gate Technology

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International Reliability Physics Symposium

作者： S. Ramey J. Hicks L. S. Liyanage S. Novak Logic Technology Development Quality and Reliability Intel Corp. Hillsboro Oregon U.S.A.

ISBN: (纸本)9781479933181

BTI recovery in tri-gate devices matches data and model predictions from planar devices, indicating a consistent physical basis for the mechanism and no influence from transistor architecture features such as crystal orientation, confinement, and vertical sidewalls. This consistency enables extending existing models established on planar devices to capture temperature and voltage dependencies of recovery. A new experimental technique allows extraction of an effective activation energy for recovery. The observation of complete recovery demonstrates that no permanent damage occurs during stress.

关键词： 22nm Tri-gate technology model predictions planar devices

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Valence band offset at amorphous boron carbide / silicon interfaces

Valence band offset at amorphous boron carbide / silicon int...

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2013 MRS Spring Meeting

作者： King, Sean W. French, Marc Jaehnig, Milt Kuhn, Markus Logic Technology Development Intel Corporation Hillsboro OR 97124 United States

In order to understand the fundamental charge transport in a-B4-5C:H/Si heterostructure devices, we have utilized x-ray photoelectron spectroscopy to determine the valence band offset at interfaces formed by Plasma Enhanced Chemical Vapor Deposition of a-B4-5C:H on (100) Si. For such interfaces, we observed relatively small valence band offset values of ± 0.25 eV. Copyright © Materials Research Society 2013A.

关键词： X ray photoelectron spectroscopy

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A 22nm high performance embedded DRAM SoC technology featuring tri-gate transistors and MIMCAP COB

A 22nm high performance embedded DRAM SoC technology featuri...

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2013 Symposium on VLSI Circuits, VLSIC 2013

作者： Brain, R. Baran, A. Bisnik, N. Chen, H.-P. Choi, S.-J. Chugh, A. Fradkin, M. Glassman, T. Hamzaoglu, F. Hoggan, E. Jahan, R. Jamil, M. Jan, C.-H. Jopling, J. Kan, H. Kasim, R. Kirby, S. Lahiri, S. Lee, B.-C. Lenski, D. Limb, J. Lindert, N. Musorrafiti, M. Neulinger, J. Rockford, L. Park, J. Singh, K. Staus, C. Steigerwald, J. Turkot, B. Vandervoorn, P. Venkatesan, R. Wu, S. Yeh, J.-Y. Wang, Y. Zhang, Z. Zhang, K. Logic Technology Development Intel Corporation Hillsboro OR 97124 United States

ISBN: (纸本)9784863483484

A 22 nm generation technology is described incorporating transistor and interconnects with performance suitable for the needs of both high density DRAM and high-performance logic devices. We have integrated a 0.029 μm2 DRAM cell capable of meeting >100μs retention at 95°C. Results will be reported for a test-vehicle with best-reported array density at 17.5Mb/mm2 based on a 128Mb macro. The process technology utilizes our leading edge 22nm 3-D tri-gate transistor as described previously [1,2]. The excellent leakage and performance characteristics of tri-gate transistors have been optimized for the access transistor, while maintaining the performance needed to enable high performance circuits in the same die. A high aspect-ratio, 3-D metal-insulator-metal capacitor trench has been integrated into the ultra-low-k interlayer dielectric and Cu metallization used for interconnect stacks. The previously described 22nm logic and SoC technology has been leveraged, with a 3-D MIM capacitor included in the ultra-low-k (ULK) ILD at the same level as the Metal-2 through Metal-4 interconnects. Excellent retention capability and yield have been demonstrated. © 2013 JSAP.

关键词： System-on-chip

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Transmission fourier transform infra-red spectroscopy investigation of structure property relationships in low-k SiOxCy:H Dielectric thin films

Transmission fourier transform infra-red spectroscopy invest...

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2012 MRS Fall Meeting

作者： King, Sean W. Mays, Ebony Ege, Canay Hellgren, Niklas Xu, Jessica Li, Han Boyanov, Boyan Logic Technology Development Intel Corporation Hillsboro OR 97124 United States

ISBN: (纸本)9781632661104

In order to understand the structure property relationships for inorganic low dielectric constant (i.e. low-k) materials, transmission Fourier Transform-Infrared (FTIR) spectroscopy has been utilized to study the local bonding structure in various plasma enhanced chemically vapor deposited low-k materials in the SiOxCy:H phase diagram. The FTIR measurements were combined with additional mechanical, electrical, and optical property measurements to elucidate the structure property relationships for these materials. The combined measurements show that increased incorporation of terminal methyl bonding results in a decrease in network bonding that manifests itself in a reduction in mass density, dielectric constant, refractive index, Young's modulus and many other important material properties. © 2012 Materials Research Society.

关键词： Fourier transform infrared spectroscopy

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