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检索条件"机构=Logic Technology Development"

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A comprehensive metric for evaluating interconnect performance

A comprehensive metric for evaluating interconnect performan...

引用

IEEE International Conference on Interconnect technology

作者： I. Young K. Raol Logic Technology Development Intel Corporation Hillsboro OR USA

ISBN: (纸本)0780366786

A methodology to benchmark and develop interconnect performance is presented. The methodology uses stochastic wiring distribution model in conjunction with a performance metric to help develop and benchmark an interconnect system for a VLSI processor using CMOS technology. The importance of repeaters is clearly demonstrated as a driver to meet performance constraints.

关键词： Wiring Integrated circuit interconnections logic Measurement CMOS technology Stochastic processes Equations Iterative algorithms Stochastic systems Semiconductor device modeling

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Reliability studies on a 45nm low power system-on-chip (SoC) dual gate oxide high-k / metal gate (DG HK+MG) technology

Reliability studies on a 45nm low power system-on-chip (SoC)...

引用

Annual International Symposium on Reliability Physics

作者： C. Prasad P. Bai S. Gannavaram W. Hafez J. Hicks C.-H. Jan J. Lin M. Jones K. Komeyli R. Kotlyar K. Mistry I. Post C. Tsai Logic Technology Development Quality and Reliability Hillsboro OR USA Logic Technology Development Hillsboro OR USA Design and Technology Solutions Intel Corporation Limited Hillsboro OR USA

ISBN: (纸本)9781424454303;9781424454310

In this paper, we present extensive reliability characterization results for a novel dual gate 45 nm HK+MG technology. BTI, HCI and TDDB degradation modes on the logic and I/O transistors are studied and excellent reliability is demonstrated. Emphasis is placed on the importance of process optimizations to support robust I/O transistors while maintaining the high performance and reliability of logic transistors. Monitoring of reliability for HVM and collateral reliability are also addressed.

关键词： Power system reliability High K dielectric materials High-K gate dielectrics Degradation logic MOS devices CMOS technology Robustness Niobium compounds Titanium compounds

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Intel automation and its role in process development and high volume manufacturing

Intel automation and its role in process development and hig...

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IEEE/SEMI Conference and Workshop on Advanced Semiconductor Manufacturing

作者： C. Mouli K. Srinivasan Logic Technology Development Intel Corporation Hillsboro OR USA

In this paper, the evolution of fab automation within Intel over the past decade and its increasing role in enabling process technology development and high volume manufacturing in the era of nanotechnology is presented. Silicon manufacturing technology faces a number of challenges, which include - growing manufacturing process complexity, increasing need to be cost effective, and need for tighter process control to maintain product yield. Given these challenges, a higher level of factory automation is becoming increasingly important to maintain competitive advantage and technology leadership in the semi-conductor industry. This paper will cover four areas: a) Automation role in Intel's technology module development and manufacturing; b) Automation Capabilities roadmap which includes a historical perspective starting from 200 mm and it's evolution to the current 90/65 nm technology generations in 300 mm manufacturing c) Automation framework based architecture strategy to deliver cost-efficient technology enabling solutions; d) Intel's Next Generation Manufacturing Execution System (NGMES) migration effort and results to date. This paper is concluded by summarizing key learning to date and look-ahead on emerging challenges.

关键词： Manufacturing automation Manufacturing processes logic Costs Pulp manufacturing Automatic control Control systems Nanotechnology Moore's Law Silicon

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Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout

Tri-Gate fully-depleted CMOS transistors: fabrication, desig...

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Symposium on VLSI technology

作者： B. Doyle B. Boyanov S. Datta M. Doczy S. Hareland B. Jin J. Kavalieros T. Linton R. Rios R. Chau Logic Technology Development Intel Corporation Hillsboro OR USA

Tri-Gate fully-depleted CMOS transistors have been fabricated with various body dimensions. These experimental results and 3-D simulations are used to explore the design space for full depletion, as well as layout issues for the Tri-Gate architecture, down to 30 nm gate lengths. It is found not only that the Tri-Gate body dimensions are flexible and relaxed compared to single-gate or double-gate devices, but that the corner plays a fundamental role in determining the device I-V characteristics. The corner device not only turns on at lower voltages due to the proximity of two adjacent gates, but the DIBL of this part of the device is much smaller than the rest of the transistor. The shape of the subthreshold I-V characteristics and the degree of DIBL control, as well as the early device turn-on are also greatly affected by the degree of body corner rounding. Examination of layout issues shows that the fin-doubling approach from using a spacer printing technique results in an increase in drive current of 1.2 times that of a planar device for a given width, though the shape of the allowed Tri-Gate fins has certain restrictions.

关键词： Fabrication Transistors Implants MOS devices Space technology Space exploration Shape control Boron CMOS logic circuits CMOS technology

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Challenges and opportunities in nano-scale VLSI design

Challenges and opportunities in nano-scale VLSI design

引用

International Symposium on VLSI Design, Automation and Test

作者： K. Zhang Logic Technology Development Intel Corporation Hillsboro OR USA

Moore's law continues to drive the scaling of CMOS technology (Moore, 1965), The feature size of the transistor now has been shrunk well into nano-scale region (Bohr, 2002). A large single VLSI chip can contain over one billion transistors. The ever-increasing level of integration has enabled higher performance and richer feature sets on a single chip. This has led to the explosive growth of microelectronics industry over last decades. But as the geometry of the transistor is getting smaller and the number of transistors on a single chip grows exponentially, the power management for a state-of-the-art VLSI design has become increasingly important. To maintain the performance trend of the VLSI system as the technology scaling continues, many advanced design techniques, especially in power management, have to be employed in order to achieve a balanced design to meet platform and end-user needs.

关键词： Very large scale integration CMOS technology Transistors Energy management Power system management Moore's Law Explosives Microelectronics Geometry technology management

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A novel technique for full-wave modeling of large-scale three-dimensional high-speed on/off-chip interconnect structures

A novel technique for full-wave modeling of large-scale thre...

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International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

作者： D. Jiao M. Mazumder S. Chakravarty C. Dai M.J. Kobrinsky M.C. Harmes S. List Logic Technology Development Intel Corporation CA USA

This paper presents a novel, rigorous, and fast method for full-wave modeling of high-speed interconnect structures. In this method, the original wave propagation problem is represented into a generalized eigenvalue problem. The resulting eigenvalue representation can comprehend conductor and dielectric losses, arbitrary dielectric and conductor configurations, and arbitrary materials such as dispersive, and anisotropic media. The edge basis function is employed to accurately represent the unknown field, and the triangular element is adopted to flexibly model arbitrary geometry. A mode-matching technique applicable to lossy system is developed to solve large-scale 3D problems by using 2D-like CPU time and memory. A circuit-based extraction technique is developed to obtain S-parameters from the unknown fields. The proposed technique can generate S-parameters, full-wave RLGC, propagation constants, characteristic impedances, voltage, current, and field distributions, and hence yield a comprehensive representation of interconnect structures. Experimental and numerical results demonstrate its accuracy and efficiency.

关键词： Large-scale systems Integrated circuit interconnections Conducting materials Dielectric losses Eigenvalues and eigenfunctions Scattering parameters Dielectric materials Dispersion Anisotropic magnetoresistance Solid modeling

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Dual damascene patterning of polymer interlayer dielectrics

Dual damascene patterning of polymer interlayer dielectrics

引用

IEEE International Conference on Interconnect technology

作者： M. Hussein R. Brain R. Turkot J. Leu V. Singh S. Sivakumar Logic Technology Development Intel Corporation Hillsboro OR USA

We unveil an innovative and manufacturable process technique to pattern dual damascene structures in polymer interlayer dielectric (ILD) without the need for either a permanent hardmask or an embedded etch stop (ES) layer. We introduce a sacrificial hardmask (SAM) and a sacrificial via fill (SAVIL) material to enable the patterning process. Since the hardmask is sacrificial, it is removed at the end of the patterning process without compromising the overall dielectric value of the ILD. The utilization of the SAVIL material provided the trench lithography step with a hole-free, and planar substrate. We demonstrate patterning of dual damascene structures using SAM/SAVIL in a via-first integration scheme through a comparative patterning performance between the SAM/SAVIL-assisted dual damascene patterning and the dual hardmask approach used most in the industry.

关键词： Polymers Lithography Manufacturing processes Dielectric constant Dielectric materials High K dielectric materials Copper Simultaneous localization and mapping logic Etching

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Automated statistical process matching across the virtual fab

Automated statistical process matching across the virtual fa...

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IEEE International Symposium on Semiconductor Manufacturing

作者： Girish Nirgude Diaa Nassar Logic Technology Development Intel Corporation Hillsboro OR USA

ISBN: (纸本)9781424411412

Statistical process matching plays a central role in detecting and minimizing special and common cause variations in semiconductor manufacturing. Performing automated statistical matching across many fabs, thousands of tools and millions of data points at acceptable performance and scalability requires a complex automation infrastructure. In this paper, we cover the main features of Intel's fab automation infrastructure that facilitates a multitude of offline statistical analyses.

关键词： Manufacturing automation Semiconductor device manufacture Databases Engines Process control Data mining Decision making Manufacturing processes Data analysis logic

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Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process

Temperature Sensor Design in a High Volume Manufacturing 65n...

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Custom Integrated Circuits Conference (CICC)

作者： David E. Duarte George Geannopoulos Usman Mughal Keng L. Wong Greg Taylor Logic Technology Development Intel Corporation Hillsboro OR USA

Thermal management (TM) allows the system architect to design a cooling solution based on real-life power consumption, not peak power. The on-die thermal sensor circuit, as the core of the TM system, monitors the on-die junction temperature (Tj). We present a novel high-linearity thermal sensor topology with built-in circuit support for correction of systematic shifts in the transfer function correction. Results obtained on the 65 nm Pentiumreg4 processor demonstrate the feasibility and effectiveness of the design.

关键词： Temperature sensors Manufacturing processes CMOS process Thermal management Sensor systems Thermal sensors Circuits Energy management Power system management Cooling

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A JTAG based AC leakage self-test

A JTAG based AC leakage self-test

引用

Symposium on VLSI Circuits

作者： T. Rahal-Arabi G. Taylor Logic Technology Development Intel Corporation Hillsboro OR USA

ISBN: (纸本)4891140143

For the last decade, the manufacturing cost per transistor has been exponentially decreasing. The test cost, however, has been decreasing at a much slower rate and now occupies a significant portion of the total cost of a microprocessor. To address this problem, many companies have planned to gradually move away from functional testing to less expensive structural and system level testing. The fundamental cost difference between these techniques comes from a reduction in the number of pins directly driven by the tester. This work describes a new technique that allows a tester to determine if all of the pins on a chip have acceptable leakage without requiring the tester to actually contact each individual pin.

关键词： Automatic testing Pins Costs Current measurement Leakage current Voltage Sampling methods logic Manufacturing System testing

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