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检索条件"机构=Logic Technology Development"

共 404 条记录，以下是131-140 订阅

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Electrical and reliability characterization of CuMn self forming barrier interconnects on low k CDO dielectrics

Electrical and reliability characterization of CuMn self for...

引用

Advanced Metallization Conference 2010

作者： Indukuri, T. Akolkar, R. Clarke, J. Genc, A. Gstrein, F. Harmes, M. Miner, B. Xia, F. Zierath, D. Balakrishnan, S. Components Research Intel Corporation United States Corporate Quality Network Intel Corporation United States Logic Technology Development Intel Corporation United States

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Porosity effects on low-k dielectric film strength and interfacial adhesion

Porosity effects on low-k dielectric film strength and inter...

引用

IEEE International Conference on Interconnect technology

作者： G. Kloster T. Scherban G. Xu J. Blaine B. Sun Y. Zhou Logic Technology Development Intel Corporation Hillsboro OR USA

The elastic modulus and hardness of low k dielectric films rapidly decrease as porosity increases. By contrast, interfacial adhesion is relatively insensitive to porosity. Adhesion energy values measured by the four-point bend method are similar for porous and non-porous films. Additionally, interfacial adhesion is much stronger for polymer films than for organosiloxane films, regardless of porosity. E-beam treatments significantly improve the modulus and hardness of porous organosiloxane films, sacrificing only a slight increase in dielectric constant. Solid-state NMR and pore size measurements indicate that the improved mechanical properties result from a cross-linking mechanism rather than macroscopic densification. TOFSIMS results show that the increased dielectric constant results from carbon loss and an increase in silanol concentration. E-beam treatments, however, do not improve interfacial adhesion significantly.

关键词： Dielectric films Adhesives Polymer films Dielectric constant Dielectric measurements Energy measurement Solid state circuits Nuclear magnetic resonance Size measurement Mechanical factors

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On-die droop detector for analog sensing of power supply noise

On-die droop detector for analog sensing of power supply noi...

引用

Symposium on VLSI Circuits

作者： A. Muhtaroglu G. Taylor T. Rahal-Arabi K. Callahan Logic Technology Development Intel Corporation Hillsboro OR USA

Understanding the supply fluctuations of various frequency harmonics is essential to maximizing microprocessor performance. Conventional methods used for analog validation of the power delivery system fall short in one or more of: a) Measurement accuracy in both frequency and time domains, especially for very high frequency noise caused by large di/dt events. The multi-GHz power supply noise attenuates very quickly away from the die. Conventional approaches of measuring the noise at the pins of the package or at the die using capacitive probes are not accurate for multi-GHz clocks. For this reason, the observability of high frequency on die noise has been very tricky. b) Implementation, e.g. delivery of analog references to multiple areas across a "noisy" die, and compactness/modularity of the measurement units. c) Automation to enable a timely volume of measurements. The efficiency of the measurements is key to correlating a particular speed path to poser supply noise. To address the above issues this paper presents an On-Die Droop Detector (ODDD), a scaleable IC solution implemented and validated on a 90 nm process, for analog sensing of differential high bandwidth supply noise.

关键词： Detectors Power supplies Noise measurement Integrated circuit noise Frequency measurement Fluctuations Microprocessors Power measurement Time measurement Pins

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A 32nm high-k and metal-gate anti-fuse array featuring a 1.01µm2 1T1C bit cell

A 32nm high-k and metal-gate anti-fuse array featuring a 1.0...

引用

Symposium on VLSI technology

作者： Sarvesh H Kulkarni Sangwoo Pae Zhanping Chen Walid Hafez Brian Pedersen Anisur Rahman Tom Tong Uddalak Bhattacharya Chia-Hong Jan Kevin Zhang Logic Technology Development Intel Corporation Hillsboro OR USA

A 1 k-bit high-density OTP (One Time Programmable)-ROM array featuring a new anti-fuse memory is presented using 32nm high-k (HK) and metal-gate (MG) CMOS process. Our 32nm HK+MG SOC process technology enables smallest reported one-transistor one-capacitor (1T1C) bit cell area measuring 1.01μm 2 . The 32-row by 32-column array with a programmable sensing scheme demonstrates yield exceeding 99.9% and robust reliability.

关键词： Arrays Sensors Programming Electric breakdown Capacitors logic gates

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Plasma-process Induced damage on 65nm logic VLSI manufacturing

Plasma-process Induced damage on 65nm logic VLSI manufacturi...

引用

2008 9th International Conference on Solid-State and Integrated-Circuit technology

作者： Jimmy Wu Howard Gan Emily Bei Forest Wang Chin Chang Liao Jay Ning Logic Technology Development Semiconductor Manufacturing International Corporation

Plasma-process induced damage (P2ID) is a serious yield and reliability concern with the continuous VLSI technical node shrinkage. In this paper, P2ID on 65nm node VLSI manufacturing development is investigated. Plasma in high-density plasma deposition (HDP), preclean of physical vapor deposition (PVD) and reactive ion etching (RIE) processes have significant negative impact on P2ID. Respective improving actions have been implemented then on following processes: pre-metal dielectric (PMD) deposition, pre-clean before Cu barrier deposition and passivation etching for Al pad. As a result, P2ID free process has been achieved for logic 65nm processes.

关键词： Plasma-process Induced damage on 65nm logic VLSI manufacturing

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Intrinsic transistor reliability improvements from 22nm tri-gate technology

Intrinsic transistor reliability improvements from 22nm tri-...

引用

Annual International Symposium on Reliability Physics

作者： S. Ramey A. Ashutosh C. Auth J. Clifford M. Hattendorf J. Hicks R. James A. Rahman V. Sharma A. St Amour C. Wiegand Logic Technology Development Quality and Reliability Portland Technology Development Intel Corporation Hillsboro OR USA

This paper highlights the intrinsic reliability capabilities of Intel's 22nm process technology, which introduced the tri-gate transistor architecture and features a 3 rd generation high-κ/metal-gate process. Results are detailed from all traditional transistor reliability mechanisms, including BTI, TDDB, SILC, and HCI. In addition, characteristics unique to this transistor architecture and process technology are described.

关键词： logic gates Transistors Integrated circuit reliability MOS devices Degradation Optimization

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CMOS scaling for the 22nm node and beyond: Device physics and technology

CMOS scaling for the 22nm node and beyond: Device physics an...

引用

International Symposium on VLSI technology, Systems and Applications

作者： Kelin J. Kuhn Logic Technology Development Intel Corporation Hillsboro OR USA

This paper reviews options for CMOS scaling for the 22nm node and beyond. Advanced transistor architectures such as ultra-thin body (UTB), FinFET, gate-all-around (GAA) and vertical options are discussed. technology challenges faced by all architectures (such as variation, resistance, and capacitance) are analyzed in relation to recent research results. The impact on the CMOS scaling roadmap of system-on-chip (SOC) technologies is reviewed.

关键词： logic gates CMOS integrated circuits Transistors System-on-a-chip Capacitance Materials Strain

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Global scaling inductor models with temperature effect

Global scaling inductor models with temperature effect

引用

International Conference on Solid-State and Integrated Circuit technology

作者： Danmy He Jenhao Cheng Leo Chen Logic Technology Development Center SMIC Shanghai China

This paper presents global lumped-element circuit models of spiral inductor and differential inductor respectively considering quality factor dependence on temperature. Metal resistance components in equivalent circuits of spiral inductor and differential inductor were adopted to reflect quality factor dependence on temperature in global model. And the global models were shown to give excellent agreement with measured data for inductors of various dimension over temperature range from -40°C to 125°C, which will facilitate customers to design circuits for worst temperature conditions in real world applications.

关键词： Inductors Spirals Q factor Temperature dependence Temperature distribution Circuits Frequency Electrical resistance measurement Temperature measurement Parasitic capacitance

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The evolution of scaling from the homogeneous era to the heterogeneous era

The evolution of scaling from the homogeneous era to the het...

引用

International Electron Devices Meeting (IEDM)

作者： Mark Bohr Logic Technology Development Intel Corporation Hillsboro OR USA

Traditional MOSFET scaling served our industry well for more than three decades by providing continuous improvements in transistor performance, power and cost. This was the era of homogeneous scaling where similar materials and device structures were scaled from generation to generation and served a wide range of integrated circuits from memory to logic applications. Traditional scaling ran out of steam in the early 2000s due mainly to the inability to further scale the SiO 2 gate oxide and this ushered in the beginning of the heterogeneous era where new materials and new device structures are being continually introduced to deliver the expected benefits of scaling. Going forward, an ever wider range of device types will be needed and the challenge we face is how to identify, develop and manufacture these revolutionary devices, and also how to integrate heterogeneous devices into compelling products.

关键词： logic gates Transistors Silicon Metals Performance evaluation High K dielectric materials

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The substrate noise detector for noise tolerant mixed-signal IC

The substrate noise detector for noise tolerant mixed-signal...

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IEEE International SOC Conference, SOCC 2003

作者： Kang, Byung-Tae Vijaykrishnan, N. Irwin, M.J. Duarte, I.D. Microsystems Design Laboratory Pennsylvania State University PA16802 United States Logic Technology Development Intel Corp. HillsboroOR97124 United States

ISBN: (纸本)0780381823

A new type of substrate noise detector is proposed. It is embedded in a mixed-signal IC and monitors the level of substrate noise. Voltage comparators are used to detect errors and a counter tracks the number of errors periodically. From the number of errors, the level of substrate noise is estimated using the probabilistic approach. This type of detector is useful in that it monitors substrate noise in real-time. Using this, various adaptive algorithms become feasible to reduce substrate noise. The details of the detector circuits are presented. © 2003 IEEE.

关键词： Threshold voltage

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