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Annual International Symposium on Reliability Physics

作者： Feng Xia Jun He Prad Prabhumirashi Anthony Schmitz Anthony Lowrie Jeff Hicks Yuriy Shusterman Ruth Brain Intel Corporation Limited Quality and Reliability Hillsboro OR USA Logic Technology Development Hillsboro OR USA

Interconnect dielectric reliability challenges increase every generation due to dimension scaling and pursuing of lower K dielectrics for performance. In this paper, TDDB reliability characteration, process innovation, process control and product validation are presented based on Intel 32 nm technology node. In definition and technology development phase, extensive characterization and process innovation are needed to enable the proper choices of materials and processes. For any given healthy process and material set, the TDDB reliability is determined by via to line and line to line space distribution, and dominated by the tail distribution of dies with small space. Although different TDDB physical models such as E, root E or other models will project very different failure probability when extrapolating from high Efield to low Efield for the main population, the choice of models makes little difference for product level failure probability from the tail population because the Efield is already in the range of that used for accelerated stressing. Since product failure rate is dominated by tail population, more focus has been given to this area in terms of process development and control. Novel self-aligned via patterning process has been developed for 32 nm technology and significantly improved via to line space and thus the low K TDDB performance. In addition, to ensure superior quality and reliability, extensive process window and product level validation through extended life test are necessary to capture and eliminate worse case process and product corners. A scaling trend and potential path to enable continuing scaling are highlighted.

关键词： Reliability Dielectrics Process control Copper Aerospace electronics Technological innovation

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Grain Engineering Approaches for High-Performance Polysilicon Thin-Film Transistor Fabrication

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MRS Online Proceedings Library 2011年第1期508卷 55-65页

作者： G. K. Giust T. W. Sigmon Memory Technology & Integration LSI Logic Santa Clara USA Advanced Process and Development Group Lawrence Livermore National Laboratory Livermore USA

Using an approach we call “grain engineering,” we discuss several techniques to control grain growth during excimer laser annealing, to create low-defect density polysilicon films. By adjusting of laser parameters, for example, we obtain polysilicon films with grain sizes of more than 9 µm, without substrate heating. These high-quality films are used in the fabrication of low-temperature unhydrogenated polysilicon thin-film transistors (TFT’s) yielding mobilities of > 260 cm2/Vs and on/off current ratios > 107. We investigate the laser recrystallization of “prepatterned” films as another technique of grain engineering. We find the performance of TFT’s fabricated in active areas that are prepatterned before laser recrystallization is dramatically improved compared to those TFT’s fabricated from the laser recrystallization of blanket polysilicon films. A novel “recessed” structure is also examined as a new grain engineering tool. By depositing a blanket silicon film on a patterned oxide layer on a heat sink, the heat flow through the continuous silicon film may be controlled during laser recrystallization to simultaneously produce adjacent regions of remarkably different grain microstructure.

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Nanoindentation and Tensile Behavior of Copper Films

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MRS Online Proceedings Library (OPL) 2011年第1期778卷 U4.3-U4.3页

作者： D. Read R. Geiss J. Ramsey T. Scherban G. Xu J. Blaine B. Miner R.D. Emery National Institute of Standards and Technology Boulder CO 80305 Reed College Portland OR 97202 Logic Technology Development Quality & Reliability Intel Corp. Hillsboro OR 97124 Components Research Intel Corp. Chandler AZ 85226

The mechanical properties of ~ 10 mm thick electroplated copper films were investigated by both nanoindentation of supported films and microtensile testing of free-standing films. By utilizing both techniques to examine the same films, the results could be directly compared to one another. Nanoindentation yield strength was found to be 5 – 15 % lower than in the microtensile case. Differences were attributed to grain size differences and, for annealed films, the presence of internal stresses in supported films only. Data from both techniques generally followed the Hall-Petch trend.

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An Analytical Study of Leibniz’s Secant and Tangent on the logical Basis of Mathematical Infinity

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Chinese Quarterly Journal of Mathematics 2011年第3期26卷 420-425页

作者： ZHU Wu-jia GONG Ning-sheng DU Guo-ping School of Information Science and Technology Nanjing University of Aeronautics and Astronautics Nanjing 210016 China State Key Laboratory of Software Development Environment Beihang University Beijing 100191 China School of Electronics and Information Engineering Nanjing University of Technology Nanjing 210009 China Institute of Modern Logic and Applications Nanjing University Nanjing 210093 China

Refs 1 and 2 provide the definition of the concepts of‘potential infinity’(poi)and actual infinity(aci);Ref 3 discusses and verifies that poi and aci are a pair of contradictory opposites without intermediate(p,-p).The second part of this paper,i.e.,§2,further discusses the manners in which a variable x approaches infinitely to its limit x0 using the poi and aci methods and concludes that,in any system compatible with both poi and aci, the two approaching manners are also a pair of contradictory opposites without intermediate (A,-A).Finally,on the basis of this conclusion,we reexamine the fundamental question of Leibniz’s Secant and Tangent Lines in calculus and the limit theory and offer our analysis and raise new questions.

关键词： calculus limit theory potential infinity actual infinity

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Mechanical Stresses in Aluminum and Copper Interconnect Lines for 0.18µm logic Technologies

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MRS Online Proceedings Library (OPL) 2011年第1期563卷 189-189页

作者： Paul R. Besser Young-Chang Joo Delrose Winter Minh Van Ngo Richard Ortega Technology Development Group of Advanced Micro Devices Inc. One AMD Place Sunnyvale CA 94088. Current address: Motorola-AMD Alliance Logic Technology 3501 Ed Bluestein Blvd MD K-10 Austin TX 78721. #AMIA Laboratories (Advanced Materials Instruments and Analysis Inc.) 7801 North Lamar Suite C-73 Austin TX 78752

The mechanical stress state of conventional Al and damascene Cu lines of a 0.18 pm logic technology flow have been determined using a novel X-Ray diffraction method that permits measurement of stress on an array of critical-dimension lines on the product die. The effect of high density plasma oxide deposition and the influence of low-K dielectrics on the stress state of the Al lines is described. The effect of materials properties and fabrication methodology on the stress state of damascene Cu lines is shown with measurement of mechanical stress and strain in passivated lines at room temperature and during annealing. The effect of underlayer on the damascene Cu stress state is also quantified.

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technology options for 22nm and beyond

Technology options for 22nm and beyond

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10th International Workshop on Junction technology, IWJT-2010

作者： Kuhn, Kelin J. Liu, Mark Y. Kennel, Harold Logic Technology Development Intel Corporation Hillsboro OR 97124 United States

ISBN: (纸本)9781424458691

This paper explores the challenges facing the 22nm process generation and beyond. CMOS transistor architectures such as ultra-thin body, FinFET, and nanowire will be compared and contrasted. Mobility enhancements such as channel stress, alternative orientations, and exotic materials will be explored. Resistance challenges will be reviewed in relation to key process techniques such as silicidation, implantation and anneal. Capacitance challenges with traditional and new architectures will be discussed in light of new materials and processing techniques. The impact of new transistor architectures and enhanced channel materials on traditional junction engineering solutions will be summarized. © 2010 IEEE.

关键词： Architecture

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Plasma enhanced atomic layer deposition of SiN:H using N2 and silane

Plasma enhanced atomic layer deposition of SiN:H using N2 an...

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作者： King, Sean W. Logic Technology Development Intel Corporation Hillsboro OR 97124 United States

As the nano-electronics industry looks to transition to both three dimensional transistor and interconnect technologies at the 4 gas / N2 plasma exposures applied in an atomic layer deposition sequence can be used to ... 详细信息

ISBN: (纸本)9781566778213

关键词： Plasma enhanced chemical vapor deposition

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Patterning integration choices for high performance interconnects

Patterning integration choices for high performance intercon...

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作者： Brain, Ruth Rockford, Lee Logic Technology Development Intel Corporation Hillsboro OR United States

ISBN: (纸本)9781617822810

Patterning integration architecture choices can significantly impact the ability to integrate low-k inter-layer dielectrics into a high density, high performance, and reliable interconnect stack. This paper discusses the scalability of the self-aligned via process that has been described in previous papers [1,2] and compares other architectures that can be used to enable low-k integration. We demonstrate the extendibility of self-aligned via process to address the increasingly difficult problem of via-to-metal shorting at tight pitches with fully integrated 87nm pitch data on low-k ILD material.

关键词： Integration

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Plasma Enhanced Atomic Layer Deposition of SiN:H Using N2 and Silane

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ECS Transactions 2011年第2期33卷

作者： Sean King Logic Technology Development Intel Corporation 5200 NE Elam Young Parkway Hillsboro Oregon 97124

As the nano-electronics industry looks to transition to both three dimensional transistor and interconnect technologies at the < 22 nm node, highly conformal dielectric coatings with precise thickness control are increasingly being demanded. Plasma Enhanced Chemical Vapor Deposition (PECVD) currently fills this role for most applications requiring low temperature processing, but does not always meet step coverage and thickness precision requirements. We present results for a hybrid technique, Plasma Enhanced Atomic Layer Deposition (PEALD), that utilizes typical PECVD process gases and tooling while delivering improved topography coverage and thickness control. Specifically, we show that alternating SiH4 gas / N2 plasma exposures applied in an atomic layer deposition sequence can be used to deposit SiN films in a self limiting fashion.

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Rigidity Percolation in Plasma Enhanced Chemical Vapor Deposited a-SiC:H Thin Films

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ECS Transactions 2011年第8期33卷

作者： Sean King Jeff Bielefeld Logic Technology Development Intel Corporation 5200 NE Elam Young Parkway Hillsboro Oregon 97124 Intel Corporation

Plasma Enhanced Chemically Vapor Deposited SiC:H thin films are compelling materials for both semiconductor nano-electronic and MEMS/NEMS technologies due to the extreme chemical inertness of this material and the ability to tune a variety of material properties across an extreme range of values. As one example of the latter, we demonstrate that using PECVD the dielectric constant and Young's modulus of SiC:H thin films can be varied from < 3 to > 7 and < 10 GPa to > 200 GPa respectively. Utilizing Fourier Infrared-Transform Spectroscopy, we show that this remarkable range in materials properties is achieved primarily via the incorporation of terminal hydrogen groups which lowers the overall connectivity of the Si-C network bonding. We find that once the average network coordination number for Si and C falls below 2.6, the SiC network becomes under constrained and there is a loss of rigidity percolating through the system thus limiting the range of materials properties that can be achieved in this system.

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