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检索条件"机构=Logic Technology Development"
404 条 记 录,以下是11-20 订阅
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Intel PowerVia technology: Backside Power Delivery for High Density and High-Performance Computing
Intel PowerVia Technology: Backside Power Delivery for High ...
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2023 IEEE Symposium on VLSI technology and Circuits, VLSI technology and Circuits 2023
作者: Hafez, W. Agnihotri, P. Asoro, M. Aykol, M. Bains, B. Bambery, R. Bapna, M. Barik, A. Chatterjee, A. Chiu, P.C. Chu, T. Firby, C. Fischer, K. Fradkin, M. Greve, H. Gupta, A. Haralson, E. Haran, M. Hicks, J. Illa, A. Jang, M. Klopcic, S. Kobrinsky, M. Kuns, B. Lai, H.-H. Lanni, G. Lee, S.-H. Lindert, N. Lo, C.-L. Luo, Y. Malyavanatham, G. Marinkovic, B. Maymon, Y. Nabors, M. Neirynck, J. Packan, P. Paliwal, A. Pantisano, L. Paulson, L. Penmatsa, P. Prasad, C. Puls, C. Rahman, T. Ramaswamy, R. Samant, S. Sell, B. Sethi, K. Shah, F. Shamanna, M. Shang, K. Li, Q. Sibakoti, M. Stoeger, J. Strutt, N. Thirugnanasambandam, R. Tsai, C. Wang, X. Wang, A. Wu, S.-J. Xu, Q. Zhong, X.-H. Natarajan, S. Intel Corporation Logic Technology Development HillsboroOR United States
This paper presents a high-yielding backside power delivery (BPD) technology, PowerVia, implemented on Intel 4 finFET process. PowerVia more directly integrates power delivery to the transistor as compared to publishe... 详细信息
来源: 评论
SRAM design in nano-scale CMOS technologies (Invited)
SRAM design in nano-scale CMOS technologies (Invited)
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2012 Symposium on VLSI technology, VLSIT 2012
作者: Zhang, Kevin Karl, Eric Wang, Yih Logic Technology Development Intel Corporation Hillsboro OR United States
SRAM scaling has become increasingly challenging in meeting both power and density requirements. Critical circuit technologies along with key process advancement are discussed in enabling SRAM scaling to continue to f... 详细信息
来源: 评论
Carbon doped oxide (CDO) film development and integration challenges
Carbon doped oxide (CDO) film development and integration ch...
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Advanced Metallization Conference 2003, AMC 2003
作者: Andideh, Eb Moon, Peter Jain, Ajay Kloster, Grant Jan, Chia-Hong Logic Technology Development Intel Corporation Hillsboro OR United States
Carbon doped oxide (CDO) ILD film, using organosilane precursors, has been successfully integrated in 90 nm technology at Intel on 5 out of 7 layers of the interconnects. Deposition processes and approaches to lower t... 详细信息
来源: 评论
Design-technology Co-Optimization of Anti-Fuse Memory on Intel 22nm FinFET technology  65
Design-Technology Co-Optimization of Anti-Fuse Memory on Int...
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65th Annual IEEE International Electron Devices Meeting, IEDM 2019
作者: Chao, Yu-Lin Su, Chen-Yi Ramey, Stephen M. Bhattacharya, Uddalak Sell, Bernhard Zhang, Ying Kulkarni, Sarvesh H. Cha, Soonwoo Paulson, Leif R. Rajarshi, Salil M. Bloomstrom, Jason Liu, Guannan Armstrong, Mark Li, Jiabo Logic Technology Development Intel Corporation HillsboroOR United States
Design-technology co-optimization of Intel's first FinFET Anti-Fuse (AF) memory using 22FFL technology is reported. The nMOS based 1T1C bit cell containing TG and TnG is sized to satisfy electrical performance, pr... 详细信息
来源: 评论
Recent advances in computer/communications industry  10
Recent advances in computer/communications industry
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10th International Conference on Microelectronics, ICM 1998
作者: El-Mansy, Youssef A. Logic Technology Development Intel Corporation HillsboroOR United States
来源: 评论
A new failure mechanism of gate-grounded MOSFET ESD device in 90nm technology
A new failure mechanism of gate-grounded MOSFET ESD device i...
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IEEE Conference on Electron Devices and Solid-State Circuits
作者: Zhang, Li-Fei Liao, Chin-Chang Liu, Wei Wong, Waisum Logic Technology and Development Center Semiconductor Manufacture International Corp. China
A new triggering phenomenon was observed on gate-grounded nMOS (ggnMOS) ESD device in 90nm technology. The trigger voltage has been measured at the value as low as 6V. However, the low triggering voltage does not resu... 详细信息
来源: 评论
Enhancing microprocessor immunity to power supply noise with clock/data compensation
Enhancing microprocessor immunity to power supply noise with...
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2005 Symposium on VLSI Circuits
作者: Rahal-Arabi, Tawfik Taylor, Greg Barkatullah, Javed Wong, Keng L. Ma, Matthew Logic Technology Development Desktop Platforms Group Intel Corporation
This paper demonstrates an alternative to the conventional wisdom that microprocessors require a flat impedance spectrum across a broad range of frequencies in order to deliver maximum operating frequency. Delivering ... 详细信息
来源: 评论
A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products  29
A 14 nm SoC platform technology featuring 2nd generation Tri...
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29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015
作者: Jan, C.-H. Al-Amoody, F. Chang, H.-Y. Chang, T. Chen, Y.-W. Dias, N. Hafez, W. Ingerly, D. Jang, M. Karl, E. Shi, S.K.-Y. Komeyli, K. Kilambi, H. Kumar, A. Byon, K. Lee, C.-G. Lee, J. Leo, T. Liu, P.-C. Nidhi, N. Olac-Vaw, R. Petersburg, C. Phoa, K. Prasad, C. Quincy, C. Ramaswamy, R. Rana, T. Rockford, L. Subramaniam, A. Tsai, C. Vandervoorn, P. Yang, L. Zainuddin, A. Bai, P. Logic Technology Development Intel Corporation HillsboroOR United States
A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology [5] has been optimized for density, low power and wide dynamic range. 70 nm gate pitch, 52 nm metal pitch and 0... 详细信息
来源: 评论
65nm dual damascene patterning with triple layer approach
65nm dual damascene patterning with triple layer approach
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5th International Conference on Semiconductor technology, ISTC 2006
作者: Lin, Yi Shih Chen, Chao Jung Hao, Michael Xing, GuoQiang Logic Technology Development Center Semiconductor Manufacturing International Corporation
Via-first-trench-last (VFTL) has become a popular approach to dual damascene (DD) patterning. PR remaining and PR poison issue are getting worse beyond 65nm dual damascene patterning. Tri-layer approach can provide et... 详细信息
来源: 评论
A 32nm high-k and metal-gate anti-fuse array featuring a 1.01μm 2 1T1C bit cell
A 32nm high-k and metal-gate anti-fuse array featuring a 1.0...
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2012 Symposium on VLSI technology, VLSIT 2012
作者: Kulkarni, Sarvesh H. Pae, Sangwoo Chen, Zhanping Hafez, Walid Pedersen, Brian Rahman, Anisur Tong, Tom Bhattacharya, Uddalak Jan, Chia-Hong Zhang, Kevin Logic Technology Development Intel Corporation Hillsboro OR United States
A 1 k-bit high-density OTP (One Time Programmable)-ROM array featuring a new anti-fuse memory is presented using 32nm high-k (HK) and metal-gate (MG) CMOS process. Our 32nm HK+MG SOC process technology enables smalles... 详细信息
来源: 评论