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Symposium on VLSI technology

作者： W. Hafez P. Agnihotri M. Asoro M. Aykol B. Bains R. Bambery M. Bapna A. Barik A. Chatterjee P.C. Chiu T. Chu C. Firby K. Fischer M. Fradkin H. Greve A. Gupta E. Haralson M. Haran J. Hicks A. Illa M. Jang S. Klopcic M. Kobrinsky B. Kuns H.-h. Lai G. Lanni S.-H. Lee N. Lindert C.-l. Lo Y. Luo G. Malyavanatham B. Marinkovic Y. Maymon M. Nabors J. Neirynck P. Packan A. Paliwal L. Pantisano L. Paulson P. Penmatsa C. Prasad C. Puls T. Rahman R. Ramaswamy S. Samant B. Sell K. Sethi F. Shah M. Shamanna K. Shang Q. Li M. Sibakoti J. Stoeger N. Strutt R. Thirugnanasambandam C. Tsai X. Wang A. Wang S.-j. Wu Q. Xu X.-h. Zhong S. Natarajan Logic Technology Development Intel Corporation Hillsboro Oregon USA

This paper presents a high-yielding backside power delivery (BPD) technology, PowerVia, implemented on Intel 4 finFET process. PowerVia more directly integrates power delivery to the transistor as compared to published buried power rail schemes, enabling additional wiring resources on front side for signal routing. A fabricated E-core with $\gt 90$% cell utilization showed $\gt 30$% platform voltage droop improvement and 6% frequency benefit compared to a similar design without PowerVia. Transistor performance, reliability, and fault isolation capability is detailed.

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AFM Nano-IR for Photomask in-line Defect Characterization

AFM Nano-IR for Photomask in-line Defect Characterization

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Photomask technology 2024

作者： First, Mitchell Gomar-Nadal, Elba Hsiao, Jeff Rasouli, Farhood Tavassoli, Malahat Li, Chunzeng Philips, Cassandra Osborne, Jason De Wolf, Peter Intel Mask Operations Logic Technology Development Intel Corporation Santa ClaraCA United States Bruker Nano Surfaces and Metrology 112 Robin Hill Road Santa BarbaraCA93117 United States

ISBN: (纸本)9781510681576

As high-volume manufacturing (HVM) of photomasks of various types and processes expands, defects and their origin are of particular concern. Organic materials are present in many aspects of a photomask's lifecycle, from carriers and tool hardware to resists and chemical residues. Characterization of organic materials to determine their origin and mitigate their yield impact is quintessential to throughput time (TPT). With the emergence of atomic force microscopy-infrared spectroscopy (AFM-IR) failure analysis techniques, distinguishing organic defects and thin films with high resolution is limited only by the size of the AFM probe. Using the AFM-IR lab instrument, we collect IR spectra of many common materials found in our process to build a database, allowing future defects to be matched to our known materials and general external IR databases. To expand our capabilities, an in-line automated AFM with spectra acquisition capability is required, with cleanliness and recipe reliability required for factory use. Supporting this automated toolset, an automated reporting function has been developed to quickly provide customers with a complete picture of a defect, from AFM scan to IR spectra, complete with IR imaging at wavelengths of interest. This paper seeks to decode the nature of AFM Nano-IR and its place as a critical in-line defect analysis technique to increase yield and proactively prevent excursions in the HVM environment. © 2024 SPIE.

关键词： Photomasks

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A detailed comparison of various off-state breakdown methodologies for scaled Tri-gate technologies

A detailed comparison of various off-state breakdown methodo...

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Annual International Symposium on Reliability Physics

作者： K. Joshi D. Nminibapiel M. Ghoneim D. Ali R. Ramamurthy L. Pantisano I. Meric S. Ramey Logic Technology Development Quality and Reliability Intel Corporation Hillsboro OR USA

The source-drain punch-through current in off-state TDDB stress (OSS) is shown to significantly affect off-state breakdown behavior. This paper compares various OSS methodologies available in the literature and discusses how source-to-drain punch-through affects off-state breakdown and reliability. The proposed Drain-stress with Offset (DSO) OSS methodology limits punch-through to better reflect the actual field dependence of OSS breakdown for scaled tri-gate MOSFET technologies.

关键词： MOSFET Electric breakdown Estimation High-voltage techniques Aging logic gates Reliability engineering

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2D Materials in the BEOL

2D Materials in the BEOL

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2023 IEEE Symposium on VLSI technology and Circuits, VLSI technology and Circuits 2023

作者： Naylor, C.H. Maxey, K. Jezewski, C. O'Brien, K.P. Penumatcha, A.V. Kavrik, M.S. Agrawal, B. Littlefield, C.V. Lux, J. Barley, B. Weber, J.R. Gupta, A. Sen Dorow, C.J. Arefin, N. King, S. Chebiam, R. Plombon, J. Clendenning, S.B. Avci, U.E. Kobrinsky, M. Metz, M. Intel Corporation Components Research HillsboroOR97124 United States Intel Corporation Logic Technology Development HillsboroOR97124 United States Intel Corporation Global Sourcing for Equipment and Materials HillsboroOR97124 United States

ISBN: (纸本)9784863488069

2D materials, such as Transition Metal Dichalcogenides (TMDs), have potential for large impact in future technologies due to their inherent atomic thickness. Here, we present multiple applications of 2D materials in the Back End of Line (BEOL). First, we report various 300 mm BEOL compatible growth methods for 2D materials. We reveal the ultra-scaling of interconnect barriers with a 10 Å 2D BEOL barrier yielding comparable performance to 25 Å Tantalum (Ta). Furthermore, we present a novel BEOL passivation technique for an unstable film by encapsulating it with a 2D material. Lastly, with a 300 mm BEOL grown WSe2 film, we report appreciable PMOS currents up to 15 μA/μm for future BEOL CMOS technologies. © 2023 JSAP.

关键词： Transition metals

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Reliability Studies on Advanced FinFET Transistors of the Intel 4 CMOS technology

Reliability Studies on Advanced FinFET Transistors of the In...

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Annual International Symposium on Reliability Physics

作者： M. Jamil S. Mukhopadhay M. Ghoneim A. Shailos C. Prasad I. Meric S. Ramey Logic Technology Development Quality and Reliability Intel Corporation Hillsboro Oregon U.S.A.

The Intel 4 CMOS FinFET technology delivers over 20% performance gains at iso-power over the prior generation (Intel 7). This paper reports reliability studies on the Intel 4 technology that demonstrate matched or better reliability while extending Moore's law in the areas of power, performance, and scaling over its predecessor. Industry-leading technology scaling comes with numerous challenges, including co-optimization of yield, performance, and reliability. This paper reports the development of Intel 4 technology with industry-standard reliability while delivering significant advancement in generational performance and density.

关键词： Semiconductor device modeling Measurement Moore's Law Materials reliability Performance gain CMOS technology FinFETs

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Reliability Modeling of Middle-Of-Line Interconnect Dielectrics in Advanced process nodes

Reliability Modeling of Middle-Of-Line Interconnect Dielectr...

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Annual International Symposium on Reliability Physics

作者： R. Kasim C. Lin C. Perini J. Palmer N. Gilda S. Imam J. R. Weber C. Wallace J. Hicks Logic Technology Development Quality and Reliability Intel Corporation Hillsboro OR USA TCAD Intel Corporation Hillsboro OR USA Portland Technology Development Intel Corporation Hillsboro OR USA

This paper discusses the physics and methodology for estimating the Reliability lifetime of MOL (Middle-Of-Line) dielectrics for advanced process nodes. Both intrinsic and defect reliability aspects of MOL dielectrics are investigated for accurate projection of Reliability lifetime on Intel 4 process technology. Methods to deconvolute the impact of process driven variations on intrinsic Time Dependent Dielectric Breakdown (TDDB) are presented. In addition, a new construct for targeting of the MOL process parameters is also proposed to address challenges with technology scaling and to mitigate risk with pattern fidelity driven variations.

关键词： Systematics Sociology Process control Tail Aerospace electronics Dielectrics Dielectric breakdown

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Localized thermal effects in Gate-all-around devices

Localized thermal effects in Gate-all-around devices

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Annual International Symposium on Reliability Physics

作者： Colin Landon Lei Jiang Daniel Pantuso Inanc Meric Kam Komeyli Jeffrey Hicks Daniel Schroeder Logic Technology Development Intel Corporation Hillsboro USA Corporate Quality Network Intel Corporation Hillsboro USA

Gate-all-around (GAA) devices continue the technology trends of increased localized thermal confinement and higher performance. We describe the methodology used for localized thermal analysis and data collection of temperature rise on the transistor scale and compare GAA cell thermal resistance to Fin-FET cells. We demonstrate that the implications of GAA on device temperature are not a constraint to realizing the full technology benefits with proper thermal management.

关键词： Performance evaluation Temperature distribution Thermal resistance Gallium arsenide logic gates Thermal management Nanoscale devices

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Device Design Guidelines to Boost up AC Performance of CFET (Complementary Field-Effect-Transistor)-Based Inverter

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2025年

作者： Lim, Jaehyuk Han, Donghwan Sung, Juho Yoon, Seokchan Kang, Sanghyun Kim, Gwon Baac, Hyoung Won Shin, Changhwan Sungkyunkwan University Department of Electrical and Computer Engineering Suwon16419 Korea Republic of Korea University School of Electrical Engineering Seoul02841 Korea Republic of Samsung Electronics Semiconductor Research and Development Center Logic Technology Development Team Hwaseong18448 Korea Republic of

Complementary Field-Effect Transistors (CFETs) have emerged as promising candidates for next-generation semiconductor devices. CFETs feature a structure with an NMOS (or PMOS) transistor at the bottom and a transistor of the opposite type at the top. CFETs can be classified into Fin-CFETs or GAA-CFETs based on their channel structure. In this study, we compare and analyze these two devices to determine which structure is more favorable for device scaling and which device exhibits better performance per unit area. For a reliable analysis, the threshold voltage was adjusted to be the same for all devices. Initially, to compare the DC performance, the on-state drive currents in both linear mode and saturation mode operations were extracted and compared from the IDS-vs.-VGS input-transfer characteristics. Subsequently, CMOS inverters were constructed to compare their AC performance. Six parameters were extracted and compared: high-to-low propagation delay (tpHL), falling time (tf), low-to-high propagation delay (tpLH), rising time (tr), overshoot voltage (Vov), and undershoot voltage (Vund). Based on the results, we suggest which CFET structure is more suitable for device scaling. © 1982-2012 IEEE.

关键词： CMOS integrated circuits

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Novel Cell Architectures with Back-side Transistor Contacts for Scaling and Performance

Novel Cell Architectures with Back-side Transistor Contacts ...

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2023 IEEE Symposium on VLSI technology and Circuits, VLSI technology and Circuits 2023

作者： Kobrinsky, M. Silva, J.D. Mannebach, E. Mills, S. Qader, M. Abd El Adebayo, O. Radhakrishna, N. Arkali Beasley, M. Chawla, J. Chugh, S. Dasgupta, A. Desai, U. De Re, E. Dewey, G. Edwards, T. Engel, C. Gudmundsson, V. Hicks, J. Krist, B. Mehandru, R. Meric, I. Morrow, P. Nandi, D. Patel, P. Ramamurthy, R. Samanta, D. Shoer, L. Amour, A. St Tan, L.H. Yemenicioglu, S. Wang, X. Ghani, T. Components Research Intel Corporation HillsboroOR97124 United States Logic Technology Development Intel Corporation HillsboroOR97124 United States Corporate Quality Network Intel Corporation HillsboroOR97124 United States Design Enablement Intel Corporation HillsboroOR97124 United States

ISBN: (纸本)9784863488069

PowerVia increases the efficiency of power delivery by adding back-side interconnects [1]. It also improves performance by relaxing the minimum front-side interconnect pitch and by optimizing them for signaling. Research to further improve performance and density synergistically with PowerVia includes back-side device contacts and device stacking. In this paper, we present an experimental demonstration of a novel cell architecture with back-side device contacts and back side power delivery. Keywords: back-side power delivery, back-side contacts, BSCON. © 2023 JSAP.

关键词： VLSI circuits

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Particle-conserving quantum circuit ansatz with applications in variational simulation of bosonic systems

arXiv

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arXiv 2024年

作者： Bahrami, Sina Sawaya, Nicolas Intel Corporation Logic Technology Development United States Intel Labs United States Azulene Labs Inc. HPI Biosciences Inc. United States

Constrained problems are frequently encountered in classical and quantum optimization. Particle conservation, in particular, is commonly imposed when studying energy spectra of chemical and solid state systems. Though particle number-constraining techniques have been developed for fermionic (e.g. molecular electronic structure) Hamiltonians, analogous techniques are lacking for non-binary and non-fermionic problems, as in the case of bosonic systems or classical optimization problems over integer variables. Here we introduce the binary encoded multilevel particles circuit ansatz (BEMPA)—an ansatz which preserves particle count by construction—for use in quantum variational algorithms. The key insight is to build the circuit blocks by carefully positioning a set of symmetry-preserving 2- and 3-qubit gates. We numerically analyze the problem of finding the ground state eigenvalues—via the Variational Quantum Eigensolver (VQE) algorithm—of the Bose-Hubbard Hamiltonian. For a range of model parameters spanning from Mott insulator to superfluid phase, we demonstrate that our proposed circuit ansatz finds the ground state eigenvalues within drastically shorter runtimes compared to penalty-based strategies methods. Finally, we analyze the potential resource benefits of changing the qubit encoding at the end of the optimization routine. Our results attest to the efficacy of BEMPA for simulating bosonic problems for which particle number is preserved. Copyright © 2024, The Authors. All rights reserved.

关键词： Ground state

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