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共 404 条记录，以下是11-20 订阅

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Intel PowerVia technology: Backside Power Delivery for High Density and High-Performance Computing

Intel PowerVia Technology: Backside Power Delivery for High ...

引用

2023 IEEE Symposium on VLSI technology and Circuits, VLSI technology and Circuits 2023

作者： Hafez, W. Agnihotri, P. Asoro, M. Aykol, M. Bains, B. Bambery, R. Bapna, M. Barik, A. Chatterjee, A. Chiu, P.C. Chu, T. Firby, C. Fischer, K. Fradkin, M. Greve, H. Gupta, A. Haralson, E. Haran, M. Hicks, J. Illa, A. Jang, M. Klopcic, S. Kobrinsky, M. Kuns, B. Lai, H.-H. Lanni, G. Lee, S.-H. Lindert, N. Lo, C.-L. Luo, Y. Malyavanatham, G. Marinkovic, B. Maymon, Y. Nabors, M. Neirynck, J. Packan, P. Paliwal, A. Pantisano, L. Paulson, L. Penmatsa, P. Prasad, C. Puls, C. Rahman, T. Ramaswamy, R. Samant, S. Sell, B. Sethi, K. Shah, F. Shamanna, M. Shang, K. Li, Q. Sibakoti, M. Stoeger, J. Strutt, N. Thirugnanasambandam, R. Tsai, C. Wang, X. Wang, A. Wu, S.-J. Xu, Q. Zhong, X.-H. Natarajan, S. Intel Corporation Logic Technology Development HillsboroOR United States

ISBN: (纸本)9784863488069

This paper presents a high-yielding backside power delivery (BPD) technology, PowerVia, implemented on Intel 4 finFET process. PowerVia more directly integrates power delivery to the transistor as compared to published buried power rail schemes, enabling additional wiring resources on front side for signal routing. A fabricated E-core with > 90% cell utilization showed > 30% platform voltage droop improvement and 6% frequency benefit compared to a similar design without PowerVia. Transistor performance, reliability, and fault isolation capability is detailed. © 2023 JSAP.

关键词： VLSI circuits

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SRAM design in nano-scale CMOS technologies (Invited)

SRAM design in nano-scale CMOS technologies (Invited)

引用

2012 Symposium on VLSI technology, VLSIT 2012

作者： Zhang, Kevin Karl, Eric Wang, Yih Logic Technology Development Intel Corporation Hillsboro OR United States

SRAM scaling has become increasingly challenging in meeting both power and density requirements. Critical circuit technologies along with key process advancement are discussed in enabling SRAM scaling to continue to f... 详细信息

ISBN: (纸本)9781467308458

关键词： Integrated circuit design

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Carbon doped oxide (CDO) film development and integration challenges

Carbon doped oxide (CDO) film development and integration ch...

引用

Advanced Metallization Conference 2003, AMC 2003

作者： Andideh, Eb Moon, Peter Jain, Ajay Kloster, Grant Jan, Chia-Hong Logic Technology Development Intel Corporation Hillsboro OR United States

Carbon doped oxide (CDO) ILD film, using organosilane precursors, has been successfully integrated in 90 nm technology at Intel on 5 out of 7 layers of the interconnects. Deposition processes and approaches to lower the dielectric constant (k) of the film are discussed. Improvement in thermal-mechanical (TM) properties of CDO film is explained. Integration issues, poor adhesion to etch stop layer (ESL) and poor cohesion of the CDO are presented and solution to mitigate some of the problem are implemented to certify the 90 nm generation of 300 mm wafer technology. © 2004 Materials Research Society.

关键词： Diamond like carbon films

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Design-technology Co-Optimization of Anti-Fuse Memory on Intel 22nm FinFET technology 65

Design-Technology Co-Optimization of Anti-Fuse Memory on Int...

引用

65th Annual IEEE International Electron Devices Meeting, IEDM 2019

作者： Chao, Yu-Lin Su, Chen-Yi Ramey, Stephen M. Bhattacharya, Uddalak Sell, Bernhard Zhang, Ying Kulkarni, Sarvesh H. Cha, Soonwoo Paulson, Leif R. Rajarshi, Salil M. Bloomstrom, Jason Liu, Guannan Armstrong, Mark Li, Jiabo Logic Technology Development Intel Corporation HillsboroOR United States

ISBN: (纸本)9781728140315

Design-technology co-optimization of Intel's first FinFET Anti-Fuse (AF) memory using 22FFL technology is reported. The nMOS based 1T1C bit cell containing TG and TnG is sized to satisfy electrical performance, process marginality, area, and reliability spec. With gate dielectric breakdown as the mechanism of bit storage, it is found that improved gate oxide integrity is beneficial to post-breakdown resistance and overall array yield. Special attention on well design, source/drain optimization, gate height targeting and array layout in the face of 3-dimentional resistor networks in FinFET can significantly modulate array health. A 2.8 k-bit AF array with baseline yield exceeding 99.9% at no added process cost with medium SA margin setting is demonstrated. © 2019 IEEE.

关键词： FinFET

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Recent advances in computer/communications industry 10

Recent advances in computer/communications industry

引用

10th International Conference on Microelectronics, ICM 1998

作者： El-Mansy, Youssef A. Logic Technology Development Intel Corporation HillsboroOR United States

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A new failure mechanism of gate-grounded MOSFET ESD device in 90nm technology

A new failure mechanism of gate-grounded MOSFET ESD device i...

引用

IEEE Conference on Electron Devices and Solid-State Circuits

作者： Zhang, Li-Fei Liao, Chin-Chang Liu, Wei Wong, Waisum Logic Technology and Development Center Semiconductor Manufacture International Corp. China

ISBN: (纸本)9780780393394

A new triggering phenomenon was observed on gate-grounded nMOS (ggnMOS) ESD device in 90nm technology. The trigger voltage has been measured at the value as low as 6V. However, the low triggering voltage does not result in high ESD performance as conventional theory suggested. The experimental data and simulation results have shown that this is due to the dislocation of the largest electric field from drain/junction region to the edge of LDD/pocket region. Therefore heating in the smaller LDD/pocket junction causes the early burn out. It is clarified that lower trigger voltage does not always mean to higher ESD endurance.

关键词： MOSFET devices

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Enhancing microprocessor immunity to power supply noise with clock/data compensation

Enhancing microprocessor immunity to power supply noise with...

引用

2005 Symposium on VLSI Circuits

作者： Rahal-Arabi, Tawfik Taylor, Greg Barkatullah, Javed Wong, Keng L. Ma, Matthew Logic Technology Development Desktop Platforms Group Intel Corporation

ISBN: (纸本)490078401X

This paper demonstrates an alternative to the conventional wisdom that microprocessors require a flat impedance spectrum across a broad range of frequencies in order to deliver maximum operating frequency. Delivering this impedance requires large amounts of on-die capacitance. We show that proper co-design of the clock and power distribution networks can relax this requirement, saving the area and leakage power needed for on-die decoupling. Measurements made on a 130 nm processor demonstrate the approach.

关键词： Microprocessor chips

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A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products 29

A 14 nm SoC platform technology featuring 2nd generation Tri...

引用

29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015

作者： Jan, C.-H. Al-Amoody, F. Chang, H.-Y. Chang, T. Chen, Y.-W. Dias, N. Hafez, W. Ingerly, D. Jang, M. Karl, E. Shi, S.K.-Y. Komeyli, K. Kilambi, H. Kumar, A. Byon, K. Lee, C.-G. Lee, J. Leo, T. Liu, P.-C. Nidhi, N. Olac-Vaw, R. Petersburg, C. Phoa, K. Prasad, C. Quincy, C. Ramaswamy, R. Rana, T. Rockford, L. Subramaniam, A. Tsai, C. Vandervoorn, P. Yang, L. Zainuddin, A. Bai, P. Logic Technology Development Intel Corporation HillsboroOR United States

ISBN: (纸本)9784863485020

A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology [5] has been optimized for density, low power and wide dynamic range. 70 nm gate pitch, 52 nm metal pitch and 0.0499 um2 HDC SRAM cells are the most aggressive design rules reported for 14/16 nm node SoC process to achieve Moore's Law 2x density scaling over 22 nm node. High performance NMOS/PMOS drive currents of 1.3/1.2 mA/um, respectively, have been achieved at 0.7 V and 100 nA/um off-state leakage, 37%/50% improvement over 22 nm node. Ultra-low power NMOS/PMOS drives are 0.50/0.32 mA/um at 0.7 V and 15pA/um Ioff. This technology also deploys high voltage I/O transistors to support up to 3.3 V I/O. A full suite of analog, mixed-signal and RF features are also supported. © 2015 JSAP.

关键词： System-on-chip

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65nm dual damascene patterning with triple layer approach

65nm dual damascene patterning with triple layer approach

引用

5th International Conference on Semiconductor technology, ISTC 2006

作者： Lin, Yi Shih Chen, Chao Jung Hao, Michael Xing, GuoQiang Logic Technology Development Center Semiconductor Manufacturing International Corporation

ISBN: (纸本)1566774373

Via-first-trench-last (VFTL) has become a popular approach to dual damascene (DD) patterning. PR remaining and PR poison issue are getting worse beyond 65nm dual damascene patterning. Tri-layer approach can provide etch stop layer protection, excellent substrate reflectivity control, PR remaining gain and PR poison reduction. LTO (low temperature oxide) and via fill material also became a good candidate for 193 nm anti-reflection layer and hard mask for trench etching. Topics such as performance in spin coating, trench lithography, plasma etching, will be discussed.

关键词： Nanotechnology

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A 32nm high-k and metal-gate anti-fuse array featuring a 1.01μm 2 1T1C bit cell

A 32nm high-k and metal-gate anti-fuse array featuring a 1.0...

引用

2012 Symposium on VLSI technology, VLSIT 2012

作者： Kulkarni, Sarvesh H. Pae, Sangwoo Chen, Zhanping Hafez, Walid Pedersen, Brian Rahman, Anisur Tong, Tom Bhattacharya, Uddalak Jan, Chia-Hong Zhang, Kevin Logic Technology Development Intel Corporation Hillsboro OR United States

ISBN: (纸本)9781467308458

A 1 k-bit high-density OTP (One Time Programmable)-ROM array featuring a new anti-fuse memory is presented using 32nm high-k (HK) and metal-gate (MG) CMOS process. Our 32nm HK+MG SOC process technology enables smallest reported one-transistor one-capacitor (1T1C) bit cell area measuring 1.01μm 2. The 32-row by 32-column array with a programmable sensing scheme demonstrates yield exceeding 99.9% and robust reliability. © 2012 IEEE.

关键词： System-on-chip

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