This paper presents a high-yielding backside power delivery (BPD) technology, PowerVia, implemented on Intel 4 finFET process. PowerVia more directly integrates power delivery to the transistor as compared to publishe...
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SRAM scaling has become increasingly challenging in meeting both power and density requirements. Critical circuit technologies along with key process advancement are discussed in enabling SRAM scaling to continue to f...
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Carbon doped oxide (CDO) ILD film, using organosilane precursors, has been successfully integrated in 90 nm technology at Intel on 5 out of 7 layers of the interconnects. Deposition processes and approaches to lower t...
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Design-technology co-optimization of Intel's first FinFET Anti-Fuse (AF) memory using 22FFL technology is reported. The nMOS based 1T1C bit cell containing TG and TnG is sized to satisfy electrical performance, pr...
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A new triggering phenomenon was observed on gate-grounded nMOS (ggnMOS) ESD device in 90nm technology. The trigger voltage has been measured at the value as low as 6V. However, the low triggering voltage does not resu...
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ISBN:
(纸本)9780780393394
A new triggering phenomenon was observed on gate-grounded nMOS (ggnMOS) ESD device in 90nm technology. The trigger voltage has been measured at the value as low as 6V. However, the low triggering voltage does not result in high ESD performance as conventional theory suggested. The experimental data and simulation results have shown that this is due to the dislocation of the largest electric field from drain/junction region to the edge of LDD/pocket region. Therefore heating in the smaller LDD/pocket junction causes the early burn out. It is clarified that lower trigger voltage does not always mean to higher ESD endurance.
This paper demonstrates an alternative to the conventional wisdom that microprocessors require a flat impedance spectrum across a broad range of frequencies in order to deliver maximum operating frequency. Delivering ...
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ISBN:
(纸本)490078401X
This paper demonstrates an alternative to the conventional wisdom that microprocessors require a flat impedance spectrum across a broad range of frequencies in order to deliver maximum operating frequency. Delivering this impedance requires large amounts of on-die capacitance. We show that proper co-design of the clock and power distribution networks can relax this requirement, saving the area and leakage power needed for on-die decoupling. Measurements made on a 130 nm processor demonstrate the approach.
A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology [5] has been optimized for density, low power and wide dynamic range. 70 nm gate pitch, 52 nm metal pitch and 0...
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Via-first-trench-last (VFTL) has become a popular approach to dual damascene (DD) patterning. PR remaining and PR poison issue are getting worse beyond 65nm dual damascene patterning. Tri-layer approach can provide et...
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ISBN:
(纸本)1566774373
Via-first-trench-last (VFTL) has become a popular approach to dual damascene (DD) patterning. PR remaining and PR poison issue are getting worse beyond 65nm dual damascene patterning. Tri-layer approach can provide etch stop layer protection, excellent substrate reflectivity control, PR remaining gain and PR poison reduction. LTO (low temperature oxide) and via fill material also became a good candidate for 193 nm anti-reflection layer and hard mask for trench etching. Topics such as performance in spin coating, trench lithography, plasma etching, will be discussed.
A 1 k-bit high-density OTP (One Time Programmable)-ROM array featuring a new anti-fuse memory is presented using 32nm high-k (HK) and metal-gate (MG) CMOS process. Our 32nm HK+MG SOC process technology enables smalles...
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