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Annual International Symposium on Reliability Physics

作者： Stephen Ramey Chetan Prasad Marty Agostinelli Sangwoo Pae Steven Walstra Satrajit Gupta Jeffrey Hicks Logic and Technology Development Quality and Reliability Intel Corporation Hillsboro OR USA Design Technology Solutions Intel Corporation Hillsboro OR USA

Net end-of-life aging prediction under realistic use conditions is the key objective for any product aging model. In this paper, a net degradation model is introduced and effects such as recovery, subsequent degradation, frequency, duty cycle, and recovery bias are evaluated. The high-kappa recovery behavior observed is consistent with SiO 2 gate stacks, which allows the use of SiO 2 models to predict recovery in both NMOS and PMOS high-kappa transistors.

关键词： Frequency Degradation MOSFETs Stress measurement Voltage Aging Predictive models Inverters MOS devices CMOS logic circuits

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High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors

High performance 32nm logic technology featuring 2nd generat...

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International Electron Devices Meeting (IEDM)

作者： P. Packan S. Akbar M. Armstrong D. Bergstrom M. Brazier H. Deshpande K. Dev G. Ding T. Ghani O. Golonzka W. Han J. He R. Heussner R. James J. Jopling C. Kenyon S-H. Lee M. Liu S. Lodha B. Mattis A. Murthy L. Neiberg J. Neirynck S. Pae C. Parker L. Pipes J. Sebastian J. Seiple B. Sell A. Sharma S. Sivakumar B. Song A. St. Amour K. Tone T. Troeger C. Weber K. Zhang Y. Luo S. Natarajan Logic Technology Development Intel Corporation Hillsboro OR USA Quality and Reliability Engineering Intel Corporation Hillsboro OR USA TCAD Intel Corporation. Intel Corporation Hillsboro OR USA

A 32 nm logic technology for high performance microprocessors is described. 2 nd generation high-k + metal gate transistors provide record drive currents at the tightest gate pitch reported for any 32 nm or 28 nm logic technology. NMOS drive currents are 1.62 mA/um Idsat and 0.231 mA/um Idlin at 1.0 V and 100 nA/um I off . PMOS drive currents are 1.37 mA/um Idsat and 0.240 mA/um Idlin at 1.0 V and 100 nA/um I off . The impact of SRAM cell and array size on Vccmin is reported.

关键词： logic MOS devices Capacitive sensors High K dielectric materials High-K gate dielectrics Moore's Law Silicon Helium Reliability engineering Electronic mail

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High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors

High performance 32nm logic technology featuring 2nd generat...

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2009 International Electron Devices Meeting, IEDM 2009

作者： Packan, P. Akbar, S. Armstrong, M. Bergstrom, D. Brazier, M. Deshpande, H. Dev, K. Ding, G. Ghani, T. Golonzka, O. Han, W. He, J. Heussner, R. James, R. Jopling, J. Kenyon, C. Lee, S-H. Liu, M. Lodha, S. Mattis, B. Murthy, A. Neiberg, L. Neirynck, J. Pae, S. Parker, C. Pipes, L. Sebastian, J. Seiple, J. Sell, A. Sharma, A. Sivakumar, S. Song, B. Amour, A.St. Tone, K. Troeger, T. Weber, C. Zhang, K. Luo, Y. Natarajan, S. Logic Technology Development Intel Corporation RA3-353 2501 NW 229th Ave. Hillsboro OR 97124 United States Quality and Reliability Engineering Intel Corporation RA3-353 2501 NW 229th Ave. Hillsboro OR 97124 United States TCAD Intel Corporation. RA3-353 2501 NW 229th Ave. Hillsboro OR 97124 United States

ISBN: (纸本)9781424456406

A 32nm logic technology for high performance microprocessors is described. 2nd generation high-k + metal gate transistors provide record drive currents at the tightest gate pitch reported for any 32nm or 28nm logic technology. NMOS drive currents are 1.62mA/um Idsat and 0.231mA/um Idlin at 1.0V and 100nA/um Ioff. PMOS drive currents are 1.37mA/um Idsat and 0.240mA/um Idlin at 1.0V and 100nA/um Ioff. The impact of SRAM cell and array size on Vccmin is reported. © 2009 IEEE.

关键词： Computer circuits

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Impact of Film Stress on Nanoidentation Fracture Toughness Measurements for PECVD SiNx:H Films

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ECS Meeting Abstracts 2009年第19期MA2009-01卷

作者： Sean King Jessica Xu Jennifer Huening Logic Technology Development Intel Corporation 5200 NE Elam Young Rd Hillsboro OR 97124 Intel Corporation

Abstract not Available.

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Impact of Film Stress on Nanoidentation Fracture Toughness Measurements for PECVD SiNx:H Films

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ECS Transactions 2009年第2期19卷

作者： Sean King R. Chu Jessica Xu Jennifer Huening Logic Technology Development Intel Corporation 5200 NE Elam Young Rd Hillsboro OR 97124 Intel Corporation

The apparent fracture toughness for a series of plasma enhanced chemical vapor deposition SiNx:H films with film stress skewed from 300 MPa tensile to 1 GPa compressive were measured using nanoindentation. The nanoindentation results show the measured fracture toughness for these films is a linear function of the intrinsic film stress and can cause the fracture toughness to vary from as high as > 8 MPa⋅√m for compressive films to as low as < 0.5 MPa⋅√m for tensile films. Other film properties such as density and modulus were also measured and not observed to correlate strongly with the measured fracture toughness values. Based on these results, we propose a simple method for adjusting the apparent fracture toughness measured by nanoindentation experiments to the actual intrinsic fracture toughness of the material.

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High performance Hi-K + metal gate strain enhanced transistors on (110) silicon

High performance Hi-K + metal gate strain enhanced transisto...

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2008 IEEE International Electron Devices Meeting, IEDM 2008

作者： Packan, P. Cea, S. Deshpande, H. Ghani, T. Giles, M. Golonzka, O. Hattendorf, M. Kotlyar, R. Kuhn, K. Murthy, A. Ranade, P. Shifren, L. Weber, C. Zawadzki, K. Logic Technology Development Intel Corporation Hillsboro United States

ISBN: (纸本)9781424423781

For the first time, the performance impact of (110) silicon substrates on high-k + metal gate strained 45nm node NMOS and PMOS devices is presented. Record PMOS drive currents of 1.2 mA/um at 1.0 V and 100nA/um Ioff are reported. It will be demonstrated that 2D short channel effects strongly mitigate the negative impact of (110) substrates on NMOS performance. Narrow width (110) device performance is shown and compared to (100) for the first time. Device reliability is also reported showing no fundamental issue for (110) substrates.

关键词： Substrates

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45nm high-k + metal gate strain-enhanced transistors

45nm high-k + metal gate strain-enhanced transistors

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2008 Symposium on VLSI technology Digest of Technical Papers, VLSIT

作者： Auth, C. Cappellani, A. Chun, J.-S. Dalis, A. Davis, A. Ghani, T. Glass, G. Glassman, T. Harper, M. Hattendorf, M. Hentges, P. Jaloviar, S. Joshi, S. Klaus, J. Kuhn, K. Lavric, D. Lu, M. Mariappan, H. Mistry, K. Norris, B. Rahhal-orabi, N. Ranade, P. Sandford, J. Shifren, L. Souw, V. Tone, K. Tambwe, F. Thompson, A. Towner, D. Troeger, T. Vandervoorn, P. Wallace, C. Wiedemer, J. Wiegand, C. Logic Technology Development Hillsboro OR United States PTM Intel Corp. Hillsboro OR United States

ISBN: (纸本)9781424418053

Two key process features that are used to make 45nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper. The first feature is the integration of stress-enhancement techniques with the dual metal-gate + high-k transistors. The second feature is the extension of 193nm dry lithography to the 45nm technology node pitches. Use of these features has enabled industry-leading transistor performance and the first high volume 45nm high-k + metal gate technology. © 2008 IEEE.

关键词： Transistors

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High volume manufacturing issues for on-die interconnects at the 45nm process node

High volume manufacturing issues for on-die interconnects at...

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2008 IEEE International Interconnect technology Conference, IITC

作者： Moon, Peter Logic Technology Development Intel Corporation 5200 NE Elam Young Parkway Hillsboro OR 97229 United States

ISBN: (纸本)9781424419111

High volume manufacturing (HVM) for silicon devices poses numerous challenges beyond simply designing and demonstrating a useful product. This paper describes several of those challenges using examples from Intel's HVM experience fabricating on-die interconnects for high performance logic products at the 45nm process node. ©2008 IEEE.

关键词： Product design

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Investigation of post CMP voids in narrow trenches of 65 nm technology node

Investigation of post CMP voids in narrow trenches of 65 nm ...

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7th International Conference on Semiconductor technology, ISTC 2008

作者： Ruipeng, Yang Jiaxiang, Nie Yun, Kang Weiye, He Na, Su Bonfanti, Paolo Yuhui, Hu Logic Technology Development Department Semiconductor Manufacturing International Corp. Beijing Economic-Technological Development Area No. 18 Wenchang Road China

ISBN: (纸本)9789881740816

Smaller size copper lines which are widely used in sub-65nm process suffer more serious void defects. Aiming at this problem we did some research about the void defects generated in narrow metal line after chemical mechanical polishing (CMP). SAS DOE(design of experiment) software was applied in this study and the result showed that the ECP current, seed thickness and anneal temperature strongly affected the void existence. We did further research of these key factors, analyzed the mechanism and gave new scheme that can improve the copper void condition at a low risk.

关键词： Copper

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A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171m2 SRAM cell size in a 291Mb array

A 32nm logic technology featuring 2nd-generation high-k + me...

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2008 IEEE International Electron Devices Meeting, IEDM 2008

作者： Natarajan, S. Armstrong, M. Bost, M. Brain, R. Brazier, M. Chang, C.-H. Chikarmane, V. Childs, M. Deshpande, H. Dev, K. Ding, G. Ghani, T. Golonzka, O. Han, W. He, J. Heussner, R. James, R. Jin, I. Kenyon, C. Klopcic, S. Lee, S.-H. Liu, M. Lodha, S. McFadden, B. Murthy, A. Neiberg, L. Neirynck, J. Packan, P. Pae, S. Parker, C. Pelto, C. Pipes, L. Sebastian, J. Seiple, J. Sell, B. Sivakumar, S. Song, B. Tone, K. Troeger, T. Weber, C. Yang, M. Yeoh, A. Zhang, K. Logic Technology Development United States Quality and Reliability Engineering United States TCAD Intel Corporation United States

ISBN: (纸本)9781424423781

A 32nm generation logic technology is described incorporating 2 nd-generation high-k + metal-gate technology, 193nm immersion lithography for critical patterning layers, and enhanced channel strain techniques. The transistors feature 9Å EOT high-k gate dielectric, dual band-edge workfunction metal gates, and 4th-generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. Process yield, performance and reliability are demonstrated on a 291 Mbit SRAM test vehicle, with 0.171 μm2 cell size, containing >1.9 billion transistors.

关键词： Computer circuits

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