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2008 IEEE International Interconnect technology Conference, IITC

作者： Ingerly, D. Agraharam, S. Becher, D. Chikarmane, V. Fischer, K. Grover, R. Goodner, M. Haight, S. He, J. Ibrahim, T. Joshi, S. Kothari, H. Lee, K. Lin, Y. Litteken, C. Liu, H. Mays, E. Moon, P. Mule', T. Nolen, S. Patel, N. Pradhan, S. Robinson, J. Ramanarayanan, P. Sattiraju, S. Schroeder, T. Williams, S. Yashar, P. Logic Technology Development Intel Corporation Hillsboro OR 97229 United States Materials Intel Corporation Hillsboro OR 97229 United States Quality and Reliability Intel Corporation 5200 NE Elam Young Pkwy Hillsboro OR 97229 United States

ISBN: (纸本)9781424419111

Interconnect process features are described for a 45nm high performance logic technology. Through extensive use of highly manufacturable carbon doped oxide low-k dielectric layers and aggressive scaling of the SiCN etch stop film the Metal-1 to Metal-8 interconnect stack demonstrates a 10% average capacitance reduction over the 65nm process. The interconnect stack also features a very thick Metal-9 layer to provide a low resistance path for the power and I/O routing. The combined interconnect stack provides high performance and reliability and supports a Pb-free 45nm process. ©2008 IEEE.

关键词： Copper

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BTI reliability of 45 nm high-K + metal-gate process technology

BTI reliability of 45 nm high-K + metal-gate process technol...

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Annual International Symposium on Reliability Physics

作者： S. Pae M. Agostinelli M. Brazier R. Chau G. Dewey T. Ghani M. Hattendorf J. Hicks J. Kavalieros K. Kuhn M. Kuhn J. Maiz M. Metz K. Mistry C. Prasad S. Ramey A. Roskowski J. Sandford C. Thomas J. Thomas C. Wiegand J. Wiedemer Logic Technology Development Q&R USA PTD USA Intel Corporation Hillsboro OR USA

In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized HK film stack in the early development phase exhibited pre-existing traps and large amount of hysteresis that was consistent with literature. The optimized and final HK process demonstrated NMOS and PMOS BTI on HK+MG transistors that are better than that of SiON at matched E-fields and comparable at targeted 30% higher use fields. The final process also showed no hysteresis due to fast traps thereby allowing us to characterize its intrinsic degradation mechanism. On the optimized process, NMOS BTI is attributed primarily to electron trapping in the HK bulk and HK/SiON interfacial layer (IL) regions. PMOS BTI degradation, on the other hand, is mainly interface driven and is found to be very similar to that observed on conventional SiON transistors.

关键词： High K dielectric materials High-K gate dielectrics MOS devices Gate leakage Hysteresis Leakage current Electron traps Thermal degradation Electrodes logic

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Multi-cell upset probabilities of 45nm high-k + metal gate SRAM devices in terrestrial and space environments

Multi-cell upset probabilities of 45nm high-k + metal gate S...

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46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS

作者： Seifert, N. Gill, B. Foley, K. Relangi, P. Logic Technology Development Q and R Intel Corporation Hillsboro OR 97124 United States Architecture for Quality and Reliability Intel Corporation Hillsboro OR 97124 United States Design and Technology Solutions Intel Corporation Hillsboro OR 97124 United States Stanford University Dept. of Electrical Engineering Stanford CA 94305 United States

ISBN: (纸本)9781424420506

Multi-cell soft errors are a key reliability concern for advanced memory devices. We have investigated single-bit (SBU) and multi-cell upset (MCU) rates of SRAM devices built in a 45nm high-k + metal gate (HK+MG) technology under neutron, proton and heavy-ion radiation. Our data highlight the excellent soft error reliability scaling properties of HK+MG. MCU rates were kept at 10% or less of SBU ones and bit-level SBU rates continue to decrease 2 per technology generation for terrestrial applications. SRAM upset rates in orbit are projected to be 2 to 4 orders of magnitude higher than at sea-level. A dramatic increase in MCU rates relative to SBU is projected for geosynchronous orbits, where direct ionization by heavy-ions dominates. No indication of charge amplification by parasitic bipolar devices has been observed for all investigated radiation environments. The observation that SBU error rates and small MCU error rates are elevated at locations in close proximity to well contacts for high LET values is speculated to be the result of the formation of a funnel between well contacts and sensitive drains. © 2008 IEEE.

关键词： Static random access storage

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Low-K Interconnect Stack with Thick Metal 9 Redistribution Layer and Cu Die Bump for 45nm High Volume Manufacturing

Low-K Interconnect Stack with Thick Metal 9 Redistribution L...

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IEEE International Conference on Interconnect technology

作者： D. Ingerly S. Agraharam D. Becher V. Chikarmane K. Fischer R. Grover M. Goodner S. Haight J. He T. Ibrahim S. Joshi H. Kothari K. Lee Y. Lin C. Litteken H. Liu E. Mays P. Moon T. Mule S. Nolen N. Patel S. Pradhan J. Robinson P. Ramanarayanan S. Sattiraju T. Schroeder S. Williams P. Yashar Logic Technology Development Intel Corporation Hillsboro OR USA Materials Intel Corporation Hillsboro OR USA Quality Reliability Intel Corporation Hillsboro OR USA

关键词： Resists Manufacturing processes Dielectric materials logic Inorganic materials Power distribution Robustness Polymers Moon Materials reliability

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BTI reliability of 45 nm high-k + metal-gate process technology

BTI reliability of 45 nm high-k + metal-gate process technol...

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46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS

作者： Pae, S. Agostinelli, M. Brazier, M. Chau, R. Dewey, G. Ghani, T. Hattendorf, M. Hicks, J. Kavalieros, J. Kuhn, K. Kuhn, M. Maiz, J. Metz, M. Mistry, K. Prasad, C. Ramey, S. Roskowski, A. Sandford, J. Thomas, C. Thomas, J. Wiegand, C. Wiedemer, J. Logic Technology Development Q and R Intel Corporation 5200 N.E. Elam Young Pkwy. Hillsboro OR 97124 United States PTD Intel Corporation 5200 N.E. Elam Young Pkwy. Hillsboro OR 97124 United States CR Intel Corporation 5200 N.E. Elam Young Pkwy. Hillsboro OR 97124 United States

ISBN: (纸本)9781424420506

In this paper, Bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an un-optimized HK film stack in the early development phase exhibited pre-existing traps and large amount of hysteresis that was consistent with literature. The optimized and final HK process demonstrated NMOS and PMOS BTI on HK+MG transistors that are better than that of SiON at matched E-fields and comparable at targeted 30% higher use fields. The final process also showed no hysteresis due to fast traps thereby allowing us to characterize its intrinsic degradation mechanism. On the optimized process, NMOS BTI is attributed primarily to electron trapping in the HK bulk and HK/SiON interfacial layer (IL) regions. PMOS BTI degradation, on the other hand, is mainly interface driven and is found to be very similar to that observed on conventional SiON transistors. © 2008 IEEE.

关键词： Silicon compounds

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45nm High-k+Metal Gate Strain-Enhanced Transistors

45nm High-k+Metal Gate Strain-Enhanced Transistors

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Symposium on VLSI technology

作者： C. Auth A. Cappellani J. S. Chun A. Dalis A. Davis T. Ghani G. Glass T. Glassman M. Harper M. Hattendorf P. Hentges S. Jaloviar S. Joshi J. Klaus K. Kuhn D. Lavric M. Lu H. Mariappan K. Mistry B. Norris N. Rahhal-orabi P. Ranade Logic Technology Development %PTM Intel Corp. Hillsboro OR U.S.A.

ISBN: (纸本)9781424418022

Two key process features that are used to make 45nm generation metal gate+high-k gate dielectric CMOS transistors are highlighted in this paper. The first feature is the integration of stress-enhancement techniques with the dual metal-gate+high-k transistors. The second feature is the extension of 193nm dry lithography to the 45nm technology node pitches. Use of these features has enabled industry-leading transistor performance and the first high volume 45nm high-k+metal gate technology.

关键词： Transistor Device Component gates CMOS transistor DNA Integration integration PITCHES

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Multi-cell upset probabilities of 45nm high-k + metal gate SRAM devices in terrestrial and space environments

Multi-cell upset probabilities of 45nm high-k + metal gate S...

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Annual International Symposium on Reliability Physics

作者： N. Seifert B. Gill K. Foley P. Relangi Logic Technology Development Q&R Intel Corporation Hillsboro OR USA Architecture for Quality and Reliability Intel Corporation Hillsboro OR USA Design and Technology Solutions Intel Corporation Hillsboro OR USA Department of Electrical Engineering University of Stanford Stanford CA USA

Multi-cell soft errors are a key reliability concern for advanced memory devices. We have investigated single-bit (SBU) and multi-cell upset (MCU) rates of SRAM devices built in a 45 nm high-k + metal gate (HK+MG) technology under neutron, proton and heavy-ion radiation. Our data highlight the excellent soft error reliability scaling properties of HK+MG. MCU rates were kept at 10% or less of SBU ones and bit-level SBU rates continue to decrease 2times per technology generation for terrestrial applications. SRAM upset rates in orbit are projected to be 2 to 4 orders of magnitude higher than at sea-level. A dramatic increase in MCU rates relative to SBU is projected for geosynchronous orbits, where direct ionization by heavy-ions dominates. No indication of charge amplification by parasitic bipolar devices has been observed for all investigated radiation environments. The observation that SBU error rates and small MCU error rates are elevated at locations in close proximity to well contacts for high LET values is speculated to be the result of the formation of a funnel between well contacts and sensitive drains.

关键词： High K dielectric materials High-K gate dielectrics Random access memory Error analysis Protons Space technology Neutrons Ionization Error correction codes logic devices

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The high-k solution

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IEEE SPECTRUM 2007年第10期44卷 29-35页

作者： Bohr, Mark T. Chau, Robert S. Ghani, Tahir Mistry, Kaizad Process architecture and integration Intel Transistor Transistor technology and integration Logic and technology development group

The Intel's Core 2 microprocessors, based on the latest 45-nanometer CMOS process technology have more transistors and run faster and cooler than microprocessors fabricated with the previous, 65-nm process generat... 详细信息

关键词： High K dielectric materials High-K gate dielectrics Transistors Moore's Law Microprocessors Silicon Dielectrics and electrical insulation Atomic layer deposition Electrons Chemical industry

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Temperature sensor design in a high volume manufacturing 65nm CMOS digital process 29

Temperature sensor design in a high volume manufacturing 65n...

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2007 IEEE Custom Integrated Circuits Conference, CICC

作者： Duarte, David E. Geannopoulos, George Mughal, Usman Wong, Keng L. Taylor, Greg Logic Technology Development Intel Corporation Hillsboro OR 97124 United States

ISBN: (纸本)1424407869

Thermal management (TM) allows the system architect to design a cooling solution based on real-life power consumption, not peak power. The on-die thermal sensor circuit, as the core of the TM system, monitors the on-die junction temperature (Tj). We present a novel high-linearity thermal sensor topology with built-in circuit support for correction of systematic shifts in the transfer function correction. Results obtained on the 65nm Pentium®4 Processor demonstrate the feasibility and effectiveness of the design. © 2007 IEEE.

关键词： Temperature sensors

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Reducing Variation in Advanced logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS

Reducing Variation in Advanced Logic Technologies: Approache...

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International Electron Devices Meeting (IEDM)

作者： Kelin J. Kuhn Logic Technology Development Intel Corporation Hillsboro OR USA

This paper presents an overview of process variation effects, including examples of mitigation strategies and test methods. Experimental and theoretical comparisons are presented for 45 nm and 65 nm RDF. SRAM matching and interconnect variation is discussed for both 65 nm and 45 nm, including examples of process and design mitigation strategies. Use of ring oscillators for detailed measurement of within-wafer and within-die variation is illustrated for 65 nm and 45 nm products.

关键词： CMOS logic circuits logic design CMOS technology Process design Manufacturing processes CMOS process Testing Resource description framework Random access memory Ring oscillators

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