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Intel 4 CMOS technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing

Intel 4 CMOS Technology Featuring Advanced FinFET Transistor...

引用

2022 IEEE Symposium on VLSI technology and Circuits, VLSI technology and Circuits 2022

作者： Sell, B. An, S. Armstrong, J. Bahr, D. Bains, B. Bambery, R. Bang, K. Basu, D. Bendapudi, S. Bergstrom, D. Bhandavat, R. Bhowmick, S. Buehler, M. Caselli, D. Cekli, S. Chaganti, Vrsk. Chang, Y.J. Chikkadi, K. Chu, T. Crimmins, T. Darby, G. Ege, C. Elfick, P. Elko-Hansen, T. Fang, S. Gaddam, C. Ghoneim, M. Gomez, H. Govindaraju, S. Guo, Z. Hafez, W. Haran, M. Hattendorf, M. Hu, S. Jain, A. Jaloviar, S. Jang, M. Kameswaran, J. Kapinus, V. Kennedy, A. Klopcic, S. Krishnan, D. Leib, J. Lin, Y.-T. Lindert, N. Liu, G. Loh, O. Luo, Y. Mani, S. Mleczko, M. Mocherla, S. Packan, P. Paik, M. Paliwal, A. Pandey, R. Patankar, K. Pipes, L. Plekhanov, P. Prasad, C. Prince, M. Ramalingam, G. Ramaswamy, R. Riley, J. Perez, J. R. Sanchez Sandford, J. Sathe, A. Shah, F. Shim, H. Subramanian, S. Tandon, S. Tanniru, M. Thakurta, D. Troeger, T. Wang, X. Ward, C. Welsh, A. Wickramaratne, S. Wnuk, J. Xu, S.Q. Yashar, P. Yaung, J. Yoon, K. Young, N. Intel Corporation Logic Technology Development HillsboroOR United States

ISBN: (纸本)9781665497725

A new advanced CMOS FinFET technology, Intel 4, is introduced that extends Moore's law by offering 2X area scaling of the high performance logic library and greater than 20% performance gain at iso-power over Intel 7. The scaled high-performance library offers 50nm gate pitch, 30nm fin pitch and 30nm minimum metal pitch. This node delivers 8VT (4NVT + 4PVT) spanning a range of 190mV/180mV for N/PMOS, enabling designers to choose between power and speed requirements. EUV lithography is used extensively to simplify the process flow and improve yield. The interconnect stack features 16 metal layers with enhanced copper metallurgy at critical lower layers to deliver improved electromigration (EM) and lower line resistance (LR). © 2022 IEEE.

关键词： FinFET

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An Intel 3 Advanced FinFET Platform technology for High Performance Computing and SOC Product Applications

An Intel 3 Advanced FinFET Platform Technology for High Perf...

引用

2024 IEEE Symposium on VLSI technology and Circuits, VLSI technology and Circuits 2024

作者： Hafez, W. Abanulo, D. Abdelkader, M. An, S. Auth, C. Bahr, D. Balakrishnan, V. Bambery, R. Beck, M. Bhargava, M. Bhowmick, S. Biggs-Houck, J. Birdsall, J. Caselli, D. Chang, H.-Y. Chang, Y. Chaudhuri, R. Chauhan, S. Chen, C. Chikarmane, V. Chikkadi, K. Chu, T. Connor, C. De Alba, R. Deng, Y. Destefano, C. Diana, D. Dong, Y. Elfick, P. Elko-Hansen, T. Fallahazad, B. Fang, Y. Gala, D. Garg, D. Geppert, C. Govindaraju, S. Grimm, W. Grunes, H. Guler, L. Guo, Z. Gupta, A. Hattendorf, M. Havelia, S. Hazra, J. Islam, A. Jain, A. Jaloviar, S. Jamil, M. Jang, M. Kabir, M. Kameswaran, J. Karl, E. Kelgeri, S. Kennedy, A. Kilroy, C. Kim, J. Kim, Y. Krishnan, D. Lee, G. Lee, H.-P. Li, Q. Lin, H. Luk, A. Luo, Y. MacFarlane, P. Mamun, A. Marla, K. Mayeri, D. McKenna, E. Miah, A. Mistry, K. Mleczko, M. Moon, S. Nardi, D. Natarajan, S. Nathawat, J. Nolph, C. Nugroho, C. Nyhus, P. Oni, A. Packan, P. Pak, D. Paliwal, A. Pandey, R. Paredes, I. Park, K. Paulson, L. Pierre, A. Plekhanov, P. Prasad, C. Ramaswamy, R. Riley, J. Rode, J. Russell, R. Ryu, S. Saavedra, H. Salisbury, T. Sandford, J. Shah, F. Shang, K. Shekhar, P. Shu, A. Skoug, E. Sohn, J. Song, J. Sprinkle, M. Su, J. Tan, A. Troeger, T. Tsao, R. Vaidya, A. Wallace, C. Wang, X. Wang, H. Ward, C. Wickramaratne, S. Wills, M. Wu, T. Xia-Hua, Z. Xu, S. Yashar, P. Yaung, J. Yu, Y. Zilm, M. Sell, B. Logic Technology Development Intel Corporation HillsboroOR United States

ISBN: (纸本)9798350361469

An advanced Intel 3 FinFET technology is presented that has been optimized to provide 10% logic scaling, a full node of performance improvement and improved reliability compared to Intel 4. Through transistor enhancements, interconnect optimization, and design co-optimizations, up to 18% performance gain at iso-power is achieved over Intel 4. Intel 3 additionally enables a 210nm high-density standard cell, 1.2V-native I/O transistors, deep N-well isolation, and long-channel analog devices to provide full-featured technology design capabilities. © 2024 IEEE.

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High performance Hi-K + metal gate strain enhanced transistors on (110) silicon

High performance Hi-K + metal gate strain enhanced transisto...

引用

2008 IEEE International Electron Devices Meeting, IEDM 2008

作者： Packan, P. Cea, S. Deshpande, H. Ghani, T. Giles, M. Golonzka, O. Hattendorf, M. Kotlyar, R. Kuhn, K. Murthy, A. Ranade, P. Shifren, L. Weber, C. Zawadzki, K. Logic Technology Development Intel Corporation Hillsboro United States

ISBN: (纸本)9781424423781

For the first time, the performance impact of (110) silicon substrates on high-k + metal gate strained 45nm node NMOS and PMOS devices is presented. Record PMOS drive currents of 1.2 mA/um at 1.0 V and 100nA/um Ioff are reported. It will be demonstrated that 2D short channel effects strongly mitigate the negative impact of (110) substrates on NMOS performance. Narrow width (110) device performance is shown and compared to (100) for the first time. Device reliability is also reported showing no fundamental issue for (110) substrates.

关键词： Substrates

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Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout

Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Desig...

引用

2003 Symposium on VLSI technology

作者： Doyle, B. Boyanov, B. Datta, S. Doczy, M. Hareland, S. Jin, B. Kavalieros, J. Linton, T. Rios, R. Chau, R. Components Research Logic Technology Development Intel Corporation Hillsboro OR 97124 United States TCAD Logic Technology Development Intel Corporation Hillsboro OR 97124 United States

Tri-Gate fully-depleted CMOS transistors have been fabricated with various body dimensions. These experimental results and 3-D simulations are used to explore the design space for full depletion, as well as layout issues for the Tri-Gate architecture, down to 30nm gate lengths. It is found not only that the Tri-Gate body dimensions are flexible and relaxed compared to single-gate or double-gate devices, but that the corner plays a fundamental role in determining the device I-V characteristics. The corner device not only turns on at lower voltages due to the proximity of two adjacent gates, but the DIBL of this part of the device is much smaller than the rest of the transistor. The shape of the subthreshold I-V characteristics and the degree of DIBL control, as well as the early device turn-on are also greatly affected by the degree of body corner rounding. Examination of layout issues shows that the fin-doubling approach from using a spacer printing technique results in an increase in drive current of 1.2 times that of a planar device for a given width, though the shape of the allowed Tri-Gate fins has certain restrictions.

关键词： CMOS integrated circuits

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technology options for 22nm and beyond

Technology options for 22nm and beyond

引用

10th International Workshop on Junction technology, IWJT-2010

作者： Kuhn, Kelin J. Liu, Mark Y. Kennel, Harold Logic Technology Development Intel Corporation Hillsboro OR 97124 United States

ISBN: (纸本)9781424458691

This paper explores the challenges facing the 22nm process generation and beyond. CMOS transistor architectures such as ultra-thin body, FinFET, and nanowire will be compared and contrasted. Mobility enhancements such as channel stress, alternative orientations, and exotic materials will be explored. Resistance challenges will be reviewed in relation to key process techniques such as silicidation, implantation and anneal. Capacitance challenges with traditional and new architectures will be discussed in light of new materials and processing techniques. The impact of new transistor architectures and enhanced channel materials on traditional junction engineering solutions will be summarized. © 2010 IEEE.

关键词： Architecture

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A 0.094um2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist 29

A 0.094um2 high density and aging resilient 8T SRAM with 14n...

引用

29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015

作者： Koo, Kyung-Hoae Wei, Liqiong Keane, John Bhattacharya, Uddalak Karl, Eric A. Zhang, Kevin Advanced Design Logic Technology Development Intel HillsboroOR United States

ISBN: (纸本)9784863485020

A 0.094μm2 8T SRAM bitcell is developed for a 14nm technology featuring FinFET transistors with a 70nm contacted gate pitch [1]. The bitcell and supporting circuitry are optimized for high density and aging tolerance. Supply collapse and wordline boosting techniques are applied for write VMIN assist. A delayed keeper is used for read VMIN improvement. A 400MHz VMIN of 560mV is achieved with the proposed design at -10°C in volume manufacturing. © 2015 JSAP.

关键词： FinFET

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CMOS scaling for the 22nm node and beyond: Device physics and technology

CMOS scaling for the 22nm node and beyond: Device physics an...

引用

2011 International Symposium on VLSI technology, Systems and Applications, VLSI-TSA 2011

作者： Kuhn, Kelin J. Logic Technology Development Intel Corporation Hillsboro OR 97124 United States

ISBN: (纸本)9781424484928

This paper reviews options for CMOS scaling for the 22nm node and beyond. Advanced transistor architectures such as ultra-thin body (UTB), FinFET, gate-all-around (GAA) and vertical options are discussed. technology challenges faced by all architectures (such as variation, resistance, and capacitance) are analyzed in relation to recent research results. The impact on the CMOS scaling roadmap of system-on-chip (SOC) technologies is reviewed. © 2011 IEEE.

关键词： Programmable logic controllers

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Pervasive integrated material handling in 300mm semiconductor manufacturing

Pervasive integrated material handling in 300mm semiconducto...

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2004 IEEE/SEMI - Advanced Semiconductor Manufacturing Conference and Workshop

作者： Giddings, Ross A. Hunter, Jeffrey C. Logic Technology Development Intel Corp. Hillsboro OR United States

The semiconductor industry's transition to 300mm manufacturing has created many new challenges for factory automation. The increased wafer size has introduced ergonomic concerns and operational challenges leading companies to pursue a pervasive automated lot delivery infrastructure capable of supporting lot movement and processing scenarios in both technology development and high volume manufacturing. This paper will trace the evolution in the automation of 300mm lot processing operations across the 130nm and 90nm process technology nodes in Intel's first 300mm technology development fab, and review the specific cost benefits achieved. Break-throughs in the automation of lot delivery and storage and elimination of manual lot processing tasks has demonstrated tool output increases of 50% and step cycle time reductions of 40%. Further, a direct labor savings of 10% has been obtained as compared to previous technology generations.

关键词： Semiconductor device manufacture

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Valence band offset at amorphous boron carbide / silicon interfaces

Valence band offset at amorphous boron carbide / silicon int...

引用

2013 MRS Spring Meeting

作者： King, Sean W. French, Marc Jaehnig, Milt Kuhn, Markus Logic Technology Development Intel Corporation Hillsboro OR 97124 United States

In order to understand the fundamental charge transport in a-B4-5C:H/Si heterostructure devices, we have utilized x-ray photoelectron spectroscopy to determine the valence band offset at interfaces formed by Plasma Enhanced Chemical Vapor Deposition of a-B4-5C:H on (100) Si. For such interfaces, we observed relatively small valence band offset values of ± 0.25 eV. Copyright © Materials Research Society 2013A.

关键词： X ray photoelectron spectroscopy

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A 22nm high performance embedded DRAM SoC technology featuring tri-gate transistors and MIMCAP COB

A 22nm high performance embedded DRAM SoC technology featuri...

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2013 Symposium on VLSI Circuits, VLSIC 2013

作者： Brain, R. Baran, A. Bisnik, N. Chen, H.-P. Choi, S.-J. Chugh, A. Fradkin, M. Glassman, T. Hamzaoglu, F. Hoggan, E. Jahan, R. Jamil, M. Jan, C.-H. Jopling, J. Kan, H. Kasim, R. Kirby, S. Lahiri, S. Lee, B.-C. Lenski, D. Limb, J. Lindert, N. Musorrafiti, M. Neulinger, J. Rockford, L. Park, J. Singh, K. Staus, C. Steigerwald, J. Turkot, B. Vandervoorn, P. Venkatesan, R. Wu, S. Yeh, J.-Y. Wang, Y. Zhang, Z. Zhang, K. Logic Technology Development Intel Corporation Hillsboro OR 97124 United States

ISBN: (纸本)9784863483484

A 22 nm generation technology is described incorporating transistor and interconnects with performance suitable for the needs of both high density DRAM and high-performance logic devices. We have integrated a 0.029 μm2 DRAM cell capable of meeting >100μs retention at 95°C. Results will be reported for a test-vehicle with best-reported array density at 17.5Mb/mm2 based on a 128Mb macro. The process technology utilizes our leading edge 22nm 3-D tri-gate transistor as described previously [1,2]. The excellent leakage and performance characteristics of tri-gate transistors have been optimized for the access transistor, while maintaining the performance needed to enable high performance circuits in the same die. A high aspect-ratio, 3-D metal-insulator-metal capacitor trench has been integrated into the ultra-low-k interlayer dielectric and Cu metallization used for interconnect stacks. The previously described 22nm logic and SoC technology has been leveraged, with a 3-D MIM capacitor included in the ultra-low-k (ULK) ILD at the same level as the Metal-2 through Metal-4 interconnects. Excellent retention capability and yield have been demonstrated. © 2013 JSAP.

关键词： System-on-chip

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