As the nano-electronics industry looks to transition to both three dimensional transistor and interconnect technologies at the 4 gas / N2 plasma exposures applied in an atomic layer deposition sequence can be used to ...
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The apparent fracture toughness for a series of plasma enhanced chemical vapor deposition SiNx:H films with film stress skewed from 300 MPa tensile to 1 GPa compressive were measured using nanoindentation. The nanoind...
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ISBN:
(纸本)9781566777100
The apparent fracture toughness for a series of plasma enhanced chemical vapor deposition SiNx:H films with film stress skewed from 300 MPa tensile to 1 GPa compressive were measured using nanoindentation. The nanoindentation results show the measured fracture toughness for these films is a linear function of the intrinsic film stress and can cause the fracture toughness to vary from as high as > 8 MPa·√m for compressive films to as low as
Thermal management (TM) allows the system architect to design a cooling solution based on real-life power consumption, not peak power. The on-die thermal sensor circuit, as the core of the TM system, monitors the on-d...
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CMOS technology scaling trend and latest technology innovations will be discussed first. Then the paper will focus on the challenges in several critical circuit areas, including both analog and memory for high-perform...
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The BDD- and SAT-based model checking and verification methods normally require an initial state. Here we are concerned with sequential hardware verification, where an initial state must be one of the reset states. In...
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In order to understand the structure property relationships for inorganic low dielectric constant (i.e. low-k) materials, transmission Fourier Transform-Infrared (FTIR) spectroscopy has been utilized to study the loca...
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The development of the 130nm, 90nm and 65nm nodes introduced several CMP defect challenges due to the incorporation of low-K inter-layer dielectric (ILD) and new metal materials. In addition, 45nm node is considering ...
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The development of the 130nm, 90nm and 65nm nodes introduced several CMP defect challenges due to the incorporation of low-K inter-layer dielectric (ILD) and new metal materials. In addition, 45nm node is considering metal gates, such as damascene-FUSI1, which also present unique defect performance requirements. We discuss multiple strategies to reduce CMP defects. These include optimization of surface charge for particle reduction, options to reduce metal corrosion, process conditions to minimize surface damage, and design rule changes that benefit CMP defect performance.
In this paper, we present an empirical approach for the validation of the power supply impedance model. The model is widely used to design the power delivery for high performance systems. For this purpose, several sil...
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In this paper, we present an empirical approach for the validation of the power supply impedance model. The model is widely used to design the power delivery for high performance systems. For this purpose, several silicon wafers of the Pentium® III and Pentium® 4 processors were built with various amount of decoupling. The measured data showed significant discrepancies with the model predictions and provided useful insights in investigating the model regions of validity.
A 21Mb/mm2 SRAM design using 0.0367um2 HCC bitcell on a 10nm CMOS technology is presented. Gate-modulated self-collapse (GSC) write assist is utilized to enable 175mV reduction in VMIN with minimal energy overhead. In...
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This paper presents a novel, rigorous, and fast method for full-wave modeling of high-speed interconnect structures. In this method, the original wave propagation problem is represented into a generalized eigenvalue p...
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