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检索条件"机构=Logic Technology Development"

共 404 条记录，以下是61-70 订阅

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Design and validation of the Pentium/sup /spl reg// III and Pentium/sup /spl reg// 4 processors power delivery

Design and validation of the Pentium/sup /spl reg// III and ...

引用

Symposium on VLSI Circuits

作者： T. Rahal-Arabi G. Taylor M. Ma C. Webb Intel Corporation/Logic Technology Development Intel Corporation/Logic Technology Development USA

In this paper, we present an empirical approach for the validation of the power supply impedance model. The model is widely used to design the power delivery for high performance systems. For this purpose, several silicon wafers of the Pentium/sup /spl reg// III and Pentium/sup /spl reg// 4 processors were built with various amount of decoupling. The measured data showed significant discrepancies with the model predictions and provided useful insights in investigating the model regions of validity.

关键词： Inductance Impedance Voltage Capacitance Silicon Frequency Electric resistance Circuits Resonance Regulators

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The influence of Ar sputter cleaning on NiSi formation and NiSi junction leakage

The influence of Ar sputter cleaning on NiSi formation and N...

引用

6th International Conference on Semiconductor technology, ISTC2007

作者： Yang, Rui Peng Hu, Yuhui Bonfanti, Paolo Su, Na Nie, Jiaxiang Kang, Yun Logic Technology Development Department Semiconductor Manufacturing International Corp. Economic-Technological Development Area No. 18 Wenchang Road Beijing China

ISBN: (纸本)9889884445

A method to reduce junction leakage for 65 nm products was proposed. The study focused on the impact of Ar sputter cleaning (ASC) on Nickel silicide spiking and junction leakage. It was found by TEM that spiking decrease in PMOS area by eliminating ASC before Ni deposition. As a result, junction leakage was improved. Decreasing Plasma and bias power did not have obvious improvement and spiking still existed. The supposed plasma damage model was not supported by AFM data that Si substrate roughness did not have difference between before and after ASC. Here proposed a new model.

关键词： Silicides

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Investigation of post CMP voids in narrow trenches of 65 nm technology node

Investigation of post CMP voids in narrow trenches of 65 nm ...

引用

7th International Conference on Semiconductor technology, ISTC 2008

作者： Ruipeng, Yang Jiaxiang, Nie Yun, Kang Weiye, He Na, Su Bonfanti, Paolo Yuhui, Hu Logic Technology Development Department Semiconductor Manufacturing International Corp. Beijing Economic-Technological Development Area No. 18 Wenchang Road China

ISBN: (纸本)9789881740816

Smaller size copper lines which are widely used in sub-65nm process suffer more serious void defects. Aiming at this problem we did some research about the void defects generated in narrow metal line after chemical mechanical polishing (CMP). SAS DOE(design of experiment) software was applied in this study and the result showed that the ECP current, seed thickness and anneal temperature strongly affected the void existence. We did further research of these key factors, analyzed the mechanism and gave new scheme that can improve the copper void condition at a low risk.

关键词： Copper

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Stacking faults and stress memorization technique study for n-type MOSFET performance improvement in all last High-k Metal Gate process development

Stacking faults and stress memorization technique study for ...

引用

作者： Li, Yong Sun, Hao Ju, Jianhua Logic Technology and Development Center SMIC 201203 China School of Materials Science and Eng Shanghai University 200072 China

ISBN: (纸本)9781607685395

In this paper, the stacking faults, stress memorization technique (SMT) and their impacts on n-type MOSFET device performance were studied. SMT combines source/drain deep PAI improves short channel device electron mobility 25%, Ion/Ioff curve 8% and long channel device 10% and 4%, respectively. A mechanism why SMT improves device performance in all last HKMG (High-k Metal Gate) process was proposed. During SMT anneal, poly expands much more than the hard nitride cap, the thermal stress gain from poly transformation from an elastic state to a plastic state was transferred into the channel, the stress was then memorized by the source/drain stacking faults, that were formed during the SMT anneal at deep pre-amorphous source/drain area. After poly removal, the tensile stress still exists, as it was retained by the stacking faults. The stress intensity along channel, Sxx, is the key parameter to index the stress effect on device performance improvement;it is related to poly volume and gate length. And based on this, the reasons that long channel and short channel devices performance gain are much smaller than that of the middle channel devices were also discussed. © 2014 The Electrochemical Society.

关键词： Stacking faults

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A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171m2 SRAM cell size in a 291Mb array

A 32nm logic technology featuring 2nd-generation high-k + me...

引用

2008 IEEE International Electron Devices Meeting, IEDM 2008

作者： Natarajan, S. Armstrong, M. Bost, M. Brain, R. Brazier, M. Chang, C.-H. Chikarmane, V. Childs, M. Deshpande, H. Dev, K. Ding, G. Ghani, T. Golonzka, O. Han, W. He, J. Heussner, R. James, R. Jin, I. Kenyon, C. Klopcic, S. Lee, S.-H. Liu, M. Lodha, S. McFadden, B. Murthy, A. Neiberg, L. Neirynck, J. Packan, P. Pae, S. Parker, C. Pelto, C. Pipes, L. Sebastian, J. Seiple, J. Sell, B. Sivakumar, S. Song, B. Tone, K. Troeger, T. Weber, C. Yang, M. Yeoh, A. Zhang, K. Logic Technology Development United States Quality and Reliability Engineering United States TCAD Intel Corporation United States

ISBN: (纸本)9781424423781

A 32nm generation logic technology is described incorporating 2 nd-generation high-k + metal-gate technology, 193nm immersion lithography for critical patterning layers, and enhanced channel strain techniques. The transistors feature 9Å EOT high-k gate dielectric, dual band-edge workfunction metal gates, and 4th-generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. Process yield, performance and reliability are demonstrated on a 291 Mbit SRAM test vehicle, with 0.171 μm2 cell size, containing >1.9 billion transistors.

关键词： Computer circuits

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A method to extract absorption coefficient of thin films from transmission spectra of the films on thick substrates

A method to extract absorption coefficient of thin films fro...

引用

作者： King, Sean W. Milosevic, Milan Logic Technology Development Intel Corporation Hillsboro OR 97124 United States MeV Technologies Westport CT 06880 United States

In this paper we present a method that allows extraction of the absorption coefficient of a thin film from transmittance spectrum of the film on a silicon substrate. The method essentially removes all optical effects, such as interference fringes, reflectance losses, substrate absorption, etc. The method requires that the refractive index of the film is known at one wavelength and that the thickness of the film is approximately known, both of which are generally available from ellipsometric measurements. As a by-product of the procedure, the method also extracts optical constants of the film over the entire spectral range of interest and provides improved values of thickness and refractive index over those provided by ellipsometry. © 2012 American Institute of Physics.

关键词： Thin films

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State of the art in transistors

State of the art in transistors

引用

207th ECS Meeting

作者： Bohr, Mark Logic Technology Development Intel Corporation RA3-353 5200 NE Elam Young Parkway Hillsboro OR 97124

MOS transistor scaling continues to be the key enabler for improving density and performance of microprocessors and other advanced logic products. The basic MOS scaling approach, namely reducing gate oxide thickness and gate length, is no longer adequate in itself to meet today's transistor performance and power requirements New materials, structures and techniques are being incorporated in advanced logic technologies to meet a more demanding set of transistor requirements. This paper will describe transistor innovations incorporated in Intel's latest 90 nm and 65 nm generation logic technologies and discuss how circuit power limitations will change the way we scale transistors in the future.

关键词： Transistors

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2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology

2nd generation embedded DRAM with 4X lower self refresh powe...

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28th IEEE Symposium on VLSI Circuits, VLSIC 2014

作者： Meterelliyoz, Mesut Al-Amoody, Fuad H. Arslan, Umut Hamzaoglu, Fatih Hood, Luke Lal, Manoj Miller, Jeffrey L. Ramasundar, Anand Soltman, Dan Wan, Ifar Wang, Yih Zhang, Kevin Logic Technology Development Intel Corporation Hillsboro OR United States Platform Engineering Group Intel Corporation Hillsboro OR United States

ISBN: (纸本)9781479933273

2nd generation 1Gbit 2GHz Embedded DRAM (eDRAM) with 4X lower self refresh power compared to prior generation is developed in 22nm Tri-Gate CMOS technology. Retention time has been improved by 3X (300us@95°C) by process and design optimizations. Source synchronous clocking is integrated in the design to reduce clock power without penalizing bandwidth. Charge pump power is reduced by 4X by employing comparator based regulation. Temperature controlled refresh enables minimum refresh power at all temperature conditions. © 2014 IEEE.

关键词： Clocks

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High Performance logic technology - Scaling Trend and Future Challenges

High Performance Logic Technology - Scaling Trend and Future...

引用

2001 6～(th) International Conference on Solid-State and Integrated Circuit technology

作者： Simon Yang Logic Technology Development Intel Corporation

＜正＞The 130nm Si logic technology is the latest generationbeing ramped in production on both 200mm and 300mmwafers. This technology employs CMOS transistors withphysical gate length of 70nm, physical gate dielectricthickness of 1.5nm, and full Cu multi-level interconnectfor high *** the minimum dimensionapproaching atomic scale, breakthroughs are required tomaintain the scaling *** this paper,requirements andsolution paths for scaling CMOS based logic technologybeyond 70nm generation node （＜40nm in physical gatelength） have been investigated using a combination ofsimulation, experimentation, and critical *** will be presented

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A 22nm High Performance Embedded DRAM SoC technology Featuring Tri-gate Transistors and MIMCAP COB

A 22nm High Performance Embedded DRAM SoC Technology Featuri...

引用

Symposium on VLSI Circuits

作者： R. Brain A. Baran N. Bisnik H. P. Chen S. J. Choi A. Chugh M. Fradkin T. Glassman F. Hamzaoglu E. Hoggan R. Jahan M. Jamil C. H. Jan J. Jopling H. Kan R. Kasim S. Kirby S. Lahiri B. C. Lee D. Lenski J. Limb N. Lindert Logic Technology Development Intel Corporation

ISBN: (纸本)9781467355315

A 22 nm generation technology is described incorporating transistor and interconnects with performance suitable for the needs of both high density DRAM and high-performance logic devices. We have integrated a 0.029 μm~2 DRAM cell capable of meeting >100μs retention at 95℃. Results will be reported for a test-vehicle with best-reported array density at 17.5Mb/mm~2 based on a 128Mb macro. The process technology utilizes our leading edge 22nm 3-D tri-gate transistor as described previously [1,2]. The excellent leakage and performance characteristics of tri-gate transistors have been optimized for the access transistor, while maintaining the performance needed to enable high performance circuits in the same die. A high aspect-ratio, 3-D metal-insulator-metal capacitor trench has been integrated into the ultra-low-k interlayer dielectric and Cu metallization used for interconnect stacks. The previously described 22nm logic and SoC technology has been leveraged, with a 3-D MIM capacitor included in the ultra-low-k (ULK) ILD at the same level as the Metal-2 through Metal-4 interconnects. Excellent retention capability and yield have been demonstrated.

关键词： 22nm DRAM Embedded Performance MIM Interconnect

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