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2009 IEEE International Reliability Physics Symposium, IRPS 2009

作者： Kasim, Rahim Connor, Chris Hicks, Jeff Jopling, Jason Litteken, Chris Logic Technology Development Quality and Reliability Intel Corporation 5200 N.E. ElamYoung Pkwy Hillsboro OR 97124 United States

ISBN: (纸本)0780388038

This paper addresses several key aspects of integrated reliability for the Intel 45nm logic technology with high-K metal gate (HK+MG) transistors and Pb-free packaging. Significant changes in process architecture and materials were introduced and careful integration and manufacturing innovations were needed to meet historical expectations for transistor, defect, and package reliability. Furthermore the stability of intrinsic and defect reliability performance needed to be demonstrated. Highly accelerated TDDB and bias temperature instability (BTI) tests were implemented to enable very high sampling rates, establishing stable transistor reliability in high manufacturing volumes. Integrated product defect reliability results are presented showing that the historical correlation to yield defect density for stable manufacturing processes is maintained on this generation into an even lower fail rate regime. Similarly, volume package reliability monitor data are shown validating thermo-mechanical stability of the 1st level Pb-free package interconnect. ©2009 IEEE.

关键词： Transistors

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Global Scaling Inductor Models with Temperature Effect

Global Scaling Inductor Models with Temperature Effect

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2008 9th International Conference on Solid-State and Integrated-Circuit technology

作者： Danmy He Jenhao Cheng Leo Chen Logic Technology Development Center SMIC

This paper presents global lumped-element circuit models of spiral inductor and differential inductor respectively considering quality factor dependence on *** resistance components in equivalent circuits of spiral inductor and differential inductor were adopted to reflect quality factor dependence on temperature in global *** the global models were shown to give excellent agreement with measured data for inductors of various dimension over temperature range from -40℃to 125℃,which will facilitate customers to design circuits for worst temperature conditions in real world applications.

关键词： Global Scaling Inductor Models with Temperature Effect

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Integrated TCAD and ECAD solutions - A paradigm shift

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International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2002

作者： Lee, Shiuh-Wuu Technology CAD Division Logic Technology Development Intel Corporation 2200 Mission College Blvd. Santa ClaraCA95052-8119 United States

ISBN: (纸本)4891140275

This paper highlights the emerging need for selective integration of physical-model based TCAD modeling and simulation tools that have been mostly applied to technology development with ECAD tools that have been traditionally used for product design. The emerging technology trends that lead to this paradigm shift are highlighted. The architecture and requirements of integrated TCAD-ECAD solutions are also discussed along with the infrastructure required to successfully meet this challenge. © 2002 Japan Soc. of Applied Physics.

关键词： Energy utilization

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Low-k interconnect stack with metal-insulator-metal capacitors for 22nm high volume manufacturing

Low-k interconnect stack with metal-insulator-metal capacito...

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IEEE International Conference on Interconnect technology

作者： D. Ingerly A. Agrawal R. Ascazubi A. Blattner M. Buehler V. Chikarmane B. Choudhury F. Cinnor C. Ege C. Ganpule T. Glassman R. Grover P. Hentges J. Hicks D. Jones A. Kandas H. Khan N. Lazo K. S. Lee H. Liu A. Madhavan R. McFadden T. Mule D. Parsons P. Parthangal S. Rangaraj D. Rao J. Roesler A. Schmitz M. Sharma J. Shin Y. Shusterman N. Speer P. Tiwari G. Wang P. Yashar K. Mistry Logic Technology Development Intel Corporation Hillsboro OR USA Logic Technology Development Corporate Quality Network Intel Corporation Hillsboro OR USA Logic Technology Development Assembly Test and Technology Development Intel Corporation Hillsboro OR USA

We describe interconnect features for Intel's 22nm high-performance logic technology, with metal-insulator-metal capacitors and nine layers of interconnects. Metal-1 through Metal-6 feature a new ultra-low-k carbon doped oxide (CDO) and a low-k etch stop. Metal-7 and Metal-8 use a low-k CDO. New materials and process optimization provide 13-18% capacitance improvement. Single-exposure patterning for 80nm pitch layers makes the process cost-effective.

关键词： Metals Capacitance Resistance Dielectrics Stress Integrated circuit interconnections MIM capacitors

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High Performance logic technology-Scaling Trend and Future Challenges

High Performance Logic Technology-Scaling Trend and Future C...

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2001 6th International Conference on Solid-State and Integrated Circuit technology

作者： Simon Yang Logic Technology Development Intel Corporation

The 130nm Si logic technology is the latest generation being ramped in production on both 200mm and 300mm *** technology employs CMOS transistors with physical gate length of 70nm,physical

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The Present and Future of Moore's Law

The Present and Future of Moore's Law

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2016 13th IEEE International Conference on Solid-State and Integrated Circuit technology (ICSICT)

作者： Peng Bai Logic Technology Development Intel Corporation

I will give an overview of Moore's law, its history and present, including key results and enabling innovations, and highlight technology values for the products. I will discuss challenges for continual silicon scaling and describe important vectors in advancing Moore's law in the future. I will prensent details onI ntel 14 nm technology, the current leading edge state of art So C platform technology that is based on the 2 generation Tri-Gate transistor technology and optimized for density,low power and wide dynamic range. Inte14 nm technology has 70 nm gate pitch, 52 nm metal pitch and 0.0499 um2 HDC SRAM cells that are the mos aggressive design rules reported for 14/16 nm node So C process. It has achieved true Moore's Law 2x density scaling over 22 nm node. High performance NMOS/PMOS drive currents of 1.3/1.2 mA /um, respectively, have been achieved a0.7 V and 100 nA /um off-state leakage, 37%/50% improvement over 22 nm node. Ultra-low power NMOS/PMOS drives are 0.50/0.32 mA /um at 0.7 V and 15 p A/umI off. This technology also deploys high voltage I/O transistors to support up to 3.3 V I/O. A full suite of analog, mixed-signal and RF features are also supported.

关键词： The Present and Future of Moore's Law

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Computational electromagnetics for high-frequency IC design

Computational electromagnetics for high-frequency IC design

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Antennas and Propagation Society International Symposium

作者： Dan Jiao Changhong Dai Shiuh-Wuu Lee T.R. Arabi G. Taylor Logic Technology Development Intel Corporation

ISBN: (纸本)0780383028

We first discuss the need for computational electromagnetics (CEM) in high-frequency IC design. We then review recent advances in CEM, present chip design challenges to CEM analysis, and analyze the shortcomings of current CEM methodology. We then emphasize the importance of chip-design-driven CEM development, and finally present some promising full-wave electromagnetic-based solutions that can achieve full-chip analysis and design.

关键词： Computational electromagnetics Frequency Integrated circuit interconnections Clocks Signal design Design methodology Semiconductor device measurement Electromagnetic measurements RLC circuits Electromagnetic analysis

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Challenges and characterization of 14nm N-type bulk FinFET

Challenges and characterization of 14nm N-type bulk FinFET

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China Semiconductor technology International Conference (CSTIC)

作者： Yong Li Jianhua Ju Miao Liao Logic Technology and Development Center SMIC

ISBN: (纸本)9781479972425

FinFET device has better electrostatic performance than planar device and makes devices further scaling possible. N-type bulk FinFET process challenges such as implantation induced Fin damages, Source/Darin (S/D) epitaxy and Fin profile control were discussed. Pre-Fin anti-punch trough (APT) implantation and low beam current n-type light-doped-drain (NLDD) implantation combined with optimized post-implant annealing are both benefit to eliminate or reduce the implantation induced Fin damages. Within S/D Si epitaxy process, contact resistance, resistor resistance and transistor external resistance were much reduced. With the optimized process, n-type bulk FinFET device performance was much improved. Gate oxide performance and electron mobility were compared with previous generations; swing slope and drain induced barrier lowering were also got from the IdVg curves. Some reliability evaluations such as GOI, TDDB and HCI were performed and passed the specifications. For n-type bulk FinFET further improvement directions were proposed at last.

关键词： logic gates Silicon Epitaxial growth Human computer interaction Process control MOS devices Random access memory

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Experimental validation of crosstalk simulations for on-chip interconnects at high frequencies using S-parameters

Experimental validation of crosstalk simulations for on-chip...

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IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEPS)

作者： M.J. Kobrinsky S. Chakravarty Dan Jiao M. Harmes S. List M. Mazumder Components Research Logic Technology Development Intel Corporation Hillsboro OR USA TCAD Logic Technology Development Intel Corporation Hillsboro OR USA TCAD Logic Technology Development Intel Corporation Santa Clara CA USA Components Research Logic Technology Development Intel Corporation Hillsboro OR TCAD Logic Technology Development Intel Corporation Santa Clara CA

Since advanced microprocessors are designed based on simulation tools, accurate assessments of the amount of crosstalk noise are of paramount importance to avoid logic failures and less-than-optimal designs. With increasing clock frequencies, inductive effects become more important, and the validity of assumptions commonly used in simulation tools and approaches is unclear. We compared accurate experimental S-parameters with results derived from both magneto-quasi-static and fullwave simulation tools, for simple crosstalk structures with various capacitive and inductive couplings, in the presence of parallel and orthogonal conductors. Our validation approach made possible the identification of the strengths and weaknesses of both tools as a function of frequency, which provides useful guidance to designers who have to balance the trade-offs between accuracy and computation expenses for a large variety of cases.

关键词： Crosstalk Scattering parameters Testing logic Conductors Electrical resistance measurement Noise measurement Signal processing Frequency measurement Concurrent computing

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Valence Band Offset at Amorphous Boron Carbide / Silicon Interfaces

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MRS Online Proceedings Library 2013年第1期1576卷 1-6页

作者： King, Sean W. French, Marc Jaehnig, Milt Kuhn, Markus Logic Technology Development Intel Corporation Hillsboro U.S.A.

In order to understand the fundamental charge transport in a-B4-5C:H/Si heterostructure devices, we have utilized x-ray photoelectron spectroscopy to determine the valence band offset at interfaces formed by Plasma Enhanced Chemical Vapor Deposition of a-B4-5C:H on (100) Si. For such interfaces, we observed relatively small valence band offset values of ± 0.25 eV.

关键词： x-ray photoelectron spectroscopy (XPS) electronic structure plasma-enhanced CVD (PECVD) (deposition)

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