检索结果-内蒙古大学图书馆

SAT-Based Methods for Sequential Hardware Equivalence Verification without Synchronization

Electronic Notes in Theoretical Computer Science 2003年第4期89卷 593-607页

作者： Zurab Khasidashvili Ziyad Hanna Logic and Validation Technology Design Technology Division Intel Development Center Haifa Israel

The BDD- and SAT-based model checking and verification methods normally require an initial state. Here we are concerned with sequential hardware verification, where an initial state must be one of the reset states. In practice, a reset state is not always given by the designer, and computing a reset state of a circuit is a hard problem. In this paper we propose a method allowing usage of SAT-based verification methods without a need for a user-given or a computed initial state. The idea is to employ a binary encoding of 3-valued modeling of circuits, and use the undefined state X as a reset state.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Reliability studies of a 32nm System-on-Chip (SoC) platform technology with 2nd generation high-k/metal gate transistors

Reliability studies of a 32nm System-on-Chip (SoC) platform ...

引用

Annual International Symposium on Reliability Physics

作者： A. Rahman M. Agostinelli P. Bai G. Curello H. Deshpande W. Hafez C. -H. Jan K. Komeyli J. Park K. Phoa C. Tsai J.-Y. Yeh J. Xu Logic Technology Development Quality & Reliability Intel Corporation Hillsboro OR USA Logic Technology Development Intel Corporation Hillsboro OR USA

Extensive reliability characterization of a state of the art 32nm strained HK/MG SoC technology with triple transistor architecture is presented here. BTI, HCI and TDDB degradation modes on the logic and I/O (1.2V, 1.8V and 3.3V tolerant) transistors are studied and excellent reliability is demonstrated. Importance of process optimizations to integrate robust I/O transistors without degrading performance and reliability of logic transistors emphasized. Finally, Intrinsic and defect reliability monitoring for HVM are addressed.

关键词： MOS devices Dielectrics logic gates Integrated circuit reliability Transistors Degradation

来源：评论

学校读者我要写书评

暂无评论

Etch arts of dual damascus structure and their impacts on WAT/VBD in 65nm Cu interconnects

Etch arts of dual damascus structure and their impacts on WA...

引用

ISTC/CSTIC 2009 (CISTC)

作者： Sun, Wu Chang, Shih-Mou Zhang, Hai-Yang Yin, Xiaoming Fu, Liya Han, Baodong Wang, Xinpeng Wu, Yongqin Logic Technology Development Center Semiconductor Manufacturing International Corporation BDA No. 18 Wen Chang Rd. Beijing 100176 China

ISBN: (纸本)9781615676460

In this paper, based on the via-first DD technology, we focus on the profile tuning of via and trench and the liner removal in order to optimize the trench profile. Via profile tuning include how to realize the via with the bowling profile, vertical profile and tapering profile. Trench profile tuning emphasizes the formation mechanism of bowling profile and top rounding profile. Footing profile and under-cutting profile of via bottom in liner open step is also addressed. The effect of different etching profiles on Rc, VBD (Breakdown Voltage) are examined. Results show that different via profiles have no impact on Rc, top-rounding trench-profile results in worse VBD, while under-cut & footing liner would deliver lower and higher Rc, respectively. ©The Electrochemical Society.

关键词： Tuning

来源：评论

学校读者我要写书评

暂无评论

High performance Hi-K + metal gate strain enhanced transistors on (110) silicon

High performance Hi-K + metal gate strain enhanced transisto...

引用

International Electron Devices Meeting (IEDM)

作者： P. Packan S. Cea H. Deshpande T. Ghani M. Giles O. Golonzka M. Hattendorf R. Kotlyar K. Kuhn A. Murthy P. Ranade L. Shifren C. Weber K. Zawadzki Logic Technology Development Intel Corporation Hillsboro OR USA Logic Technology Development Process Technology Modeling Intel Corporation Hillsboro OR USA

For the first time, the performance impact of (110) silicon substrates on high-k + metal gate strained 45 nm node NMOS and PMOS devices is presented. Record PMOS drive currents of 1.2 mA/um at 1.0 V and 100 nA/um Ioff are reported. It will be demonstrated that 2D short channel effects strongly mitigate the negative impact of (110) substrates on NMOS performance. Narrow width (110) device performance is shown and compared to (100) for the first time. Device reliability is also reported showing no fundamental issue for (110) substrates.

关键词： Capacitive sensors Silicon MOS devices Occupational stress Electron mobility Compressive stress Degradation High K dielectric materials High-K gate dielectrics Charge carrier processes

来源：评论

学校读者我要写书评

暂无评论

High performance logic technology-scaling trend and future challenges

High performance logic technology-scaling trend and future c...

引用

International Conference on Solid-State and Integrated Circuit technology

作者： S. Yang Logic Technology Development Intel Corporation USA

The 130 nm Si logic technology is the latest generation being ramped in production on both 200 mm and 300 mm wafers. This technology employs CMOS transistors with physical gate length of 70 nm, physical gate dielectric thickness of 1.5 nm, and full Cu multi-level interconnect for high performance. As the minimum dimension approaching atomic scale, breakthroughs are required to maintain the scaling trend. In this paper, requirements and solution paths for scaling CMOS based logic technology beyond 70 nm generation node (<40 nm in physical gate length) have been investigated using a combination of simulation, experimentation, and critical analysis. Conclusions are presented.

关键词： CMOS technology CMOS logic circuits Delay Dielectrics Isolation technology Production Frequency Transistors Analytical models MOSFETs

来源：评论

学校读者我要写书评

暂无评论

Design and validation of the core and IOs decoupling of the Pentium/spl reg/ III and Pentium/spl reg/ 4 processors

Design and validation of the core and IOs decoupling of the ...

引用

IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEPS)

作者： T. Rahal-Arabi G. Taylor M. Ma J. Jones C. Webb Logic Technology Development Intel Corporation USA

In this paper, we present the design approach and an empirical validation of the power supply decoupling network with particular emphasis on on-die capacitance. The impact of die decoupling on core performance for the 0.18 micron version of the Pentium/spl reg/ 4 has been presented previously (T. Rahal-Arabi et al, VLSI Circ. Symp. Dig. of Tech. Papers, pp. 220-223, 2002). This paper complements the previous work by presenting the design and validation approach for the IO power supply of both the Pentium/spl reg/ III and Pentium/spl reg/ 4 processors. As the Pentium/spl reg/ III processor has separate IO and core supplies, it is a more suitable vehicle for the IO validation. The design approach relies on using the power supply impedance model to determine the required decoupling. The model is widely used in the design of high speed systems (A. Waizman and Chee-Yee Chung, IEEE Conf. Electrical Perf. of Electron. Packaging, pp. 65-68, 2000) but this paper shows that it is less adequate to evaluate performance. The validation approach consists of building several silicon wafers of the Pentium/spl reg/ III and Pentium/spl reg/ 4 processors with various amounts of decoupling. Extensive measurements are then conducted at the silicon, package, and system levels.

关键词： Power supplies Power system modeling Packaging Silicon Capacitance Very large scale integration Vehicles Impedance Semiconductor device modeling Electrons

来源：评论

学校读者我要写书评

暂无评论

Cohesive strength characterization of brittle low-k films

Cohesive strength characterization of brittle low-k films

引用

IEEE International Conference on Interconnect technology

作者： Guanghai Xu E. Andideh J. Bielefeld T. Scherban Intel Corporation Logic Technology Development Hillsboro

The cohesive strength of low k dielectric films is an important property in predicting thermomechanical integrity of the Cu/low k interconnect structure. An approach to measure the cohesive strength of brittle low k films is presented, in which residual stress, elastic modulus and film thickness, are considered. The importance of residual film stress in cohesive failures is demonstrated.

关键词： Thermal stresses Residual stresses Testing Mechanical factors Tensile stress Dielectric measurements Substrates Adhesives Transistors Optical films

来源：评论

学校读者我要写书评

暂无评论

Transmission Fourier Transform Infra-red Spectroscopy Investigation of Structure Property Relationships in Low-k SiOxCy:H Dielectric Thin Films

引用

MRS Online Proceedings Library (OPL) 2013年第1期1520卷 mrsf12-1520-nn11-04-mrsf12-1520-nn11-04页

作者： Sean W. King Ebony Mays Canay Ege Niklas Hellgren Jessica Xu Han Li Boyan Boyanov Logic Technology Development Intel Corporation Hillsboro OR 97124 U.S.A.

In order to understand the structure property relationships for inorganic low dielectric constant (i.e. low-k) materials, transmission Fourier Transform-Infrared (FTIR) spectroscopy has been utilized to study the local bonding structure in various plasma enhanced chemically vapor deposited low-k materials in the SiOxCy:H phase diagram. The FTIR measurements were combined with additional mechanical, electrical, and optical property measurements to elucidate the structure property relationships for these materials. The combined measurements show that increased incorporation of terminal methyl bonding results in a decrease in network bonding that manifests itself in a reduction in mass density, dielectric constant, refractive index, Young’s modulus and many other important material properties.

关键词： dielectric properties plasma-enhanced CVD (PECVD) (deposition) infrared (IR) spectroscopy

来源：评论

学校读者我要写书评

暂无评论

Alpha-SER modeling and simulation for sub-0.25 /spl mu/m CMOS technology

Alpha-SER modeling and simulation for sub-0.25 /spl mu/m CMO...

引用

Symposium on VLSI technology

作者： Changhong Dai N. Hakim S. Hareland J. Maiz Shiuh-Wuu Lee Logic Technology Development Intel Corporation USA

Soft errors (single event upset) due to alpha particles from radioactive impurities in packaging materials were first observed on DRAMs. While terrestrial cosmic rays also cause soft errors and dominate logic circuit soft-error rate (SER), alpha-SER contributes significantly to SRAM circuit total SER and increases at a higher rate as processing technology advances to sub-0.25 /spl mu/m feature sizes where even logic nodes become susceptible to alpha strikes. In sub-0.25 /spl mu/m CMOS and beyond, with continuous reduction in supply voltage, decrease in node capacitance, and increase in chip size and transistor count, alpha-SER has become a major reliability concern for logic products. As complex logic products such as microprocessors have numerous circuit types and sizes, accurate and efficient prediction of product SER by comprehending both microscopic charge collection physics and circuit response is both critical and a challenging task. This paper presents a comprehensive modeling and simulation approach, including: (1) circuit critical charge (Qcrit) simulation methodology, (2) compact model for alpha strike charge generation and collection, and (3) statistical algorithms for FIT (failure-in-time) rate simulation. We also present compact model calibration methods and validation using Lawrence Livermore National Lab alpha beams as well as experimentally measured FIT rates of SRAMs in three technology generations. This paper reports the alpha-SER saturation effect, which is extremely critical for future technology planning. Moreover, many of the concepts and models discussed here can be extended to neutron-SER prediction.

关键词： Semiconductor device modeling Circuit simulation logic circuits CMOS logic circuits Single event upset Alpha particles Impurities Packaging Radioactive materials Cosmic rays

来源：评论

学校读者我要写书评

暂无评论

Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology

Characterization of SILC and its end-of-life reliability ass...

引用

Annual International Symposium on Reliability Physics

作者： S. Pae T. Ghani M. Hattendorf J. Hicks J. Jopling J. Maiz K. Mistry J. O'Donnell C. Prasad J. Wiedemer J. Xu Logic Technology Development Q&R Intel Corporation Hillsboro OR USA Portland Technology Development Hillsboro OR Intel Corporation Logic Technology Development Q&R Hillsboro USA Intel Corporation Logic Technology Development Q&R

Stress induced leakage current (SILC) has been observed on non-optimized high-K (HK) and metal-gate (MG) transistors. Large NMOS PBTI degradation and correlation to SILC increase on such gate stack is a result of large trap generations in the bulk-HK. This poses a long term reliability concern on product standby power and can limit the operating voltage if not suppressed. On an optimized HK+MG process, we demonstrate that SILC has been suppressed. The transistor level SILC data, model and product burn-in stress data support this. With optimized process, SILC has no impact on products made of 45 nm HK+MG transistors.

关键词： High K dielectric materials High-K gate dielectrics Stress MOS devices Gate leakage Electron traps Leakage current Degradation Voltage Transistors

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：