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Device Design Guidelines to Boost up AC Performance of CFET (Complementary Field-Effect-Transistor)-Based Inverter

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2025年

作者： Lim, Jaehyuk Han, Donghwan Sung, Juho Yoon, Seokchan Kang, Sanghyun Kim, Gwon Baac, Hyoung Won Shin, Changhwan Sungkyunkwan University Department of Electrical and Computer Engineering Suwon16419 Korea Republic of Korea University School of Electrical Engineering Seoul02841 Korea Republic of Samsung Electronics Semiconductor Research and Development Center Logic Technology Development Team Hwaseong18448 Korea Republic of

Complementary Field-Effect Transistors (CFETs) have emerged as promising candidates for next-generation semiconductor devices. CFETs feature a structure with an NMOS (or PMOS) transistor at the bottom and a transistor of the opposite type at the top. CFETs can be classified into Fin-CFETs or GAA-CFETs based on their channel structure. In this study, we compare and analyze these two devices to determine which structure is more favorable for device scaling and which device exhibits better performance per unit area. For a reliable analysis, the threshold voltage was adjusted to be the same for all devices. Initially, to compare the DC performance, the on-state drive currents in both linear mode and saturation mode operations were extracted and compared from the IDS-vs.-VGS input-transfer characteristics. Subsequently, CMOS inverters were constructed to compare their AC performance. Six parameters were extracted and compared: high-to-low propagation delay (tpHL), falling time (tf), low-to-high propagation delay (tpLH), rising time (tr), overshoot voltage (Vov), and undershoot voltage (Vund). Based on the results, we suggest which CFET structure is more suitable for device scaling. © 1982-2012 IEEE.

关键词： CMOS integrated circuits

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Dummy poly removal impact factors and improvement in HKMG last process

Dummy poly removal impact factors and improvement in HKMG la...

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作者： Zeng, Yizhi Zhao, Jie Gao, Hanjie Awuti, Kurban Song, Woeiji Yu, Shaofeng Zhang, Qin Lin, Yihui Liu, Jialei Liu, H.X. Logic Technology and Development Center SMIC 201312 China

ISBN: (纸本)9781607685395

For 20/16nm HK-last and MG-last process, Dummy poly is removed by Wet process. This paper studies the factors impacting the dummy poly removal process, and presents some models to explain the impacting factors. Implant process is one of main factors influencing dummy poly removal capability because the differences of implant ions and doping amount into dummy poly induce difference of poly removal rate by wet process. We also study poly surface single clean, multiple clean and thermal process. Based on the model, we plan N-type doping poly and P-type doping poly with different ion doping amounts on blank wafer and 20nm structure wafers to evaluate dummy poly removal. We find dummy poly removal rate is different between N-type doping poly and P-type doping poly, and receive different dummy poly removal trend by ion amount on N-type doping poly and P-type doping poly. The model can help to improve dummy poly removal process control. © 2014 The Electrochemical Society.

关键词： Ions

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A new failure mechanism of gate-grounded MOSFET ESD device in 90nm technology

A new failure mechanism of gate-grounded MOSFET ESD device i...

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IEEE Conference on Electron Devices and Solid-State Circuits

作者： Zhang, Li-Fei Liao, Chin-Chang Liu, Wei Wong, Waisum Logic Technology and Development Center Semiconductor Manufacture International Corp. China

ISBN: (纸本)9780780393394

A new triggering phenomenon was observed on gate-grounded nMOS (ggnMOS) ESD device in 90nm technology. The trigger voltage has been measured at the value as low as 6V. However, the low triggering voltage does not result in high ESD performance as conventional theory suggested. The experimental data and simulation results have shown that this is due to the dislocation of the largest electric field from drain/junction region to the edge of LDD/pocket region. Therefore heating in the smaller LDD/pocket junction causes the early burn out. It is clarified that lower trigger voltage does not always mean to higher ESD endurance.

关键词： MOSFET devices

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65nm dual damascene patterning with triple layer approach

65nm dual damascene patterning with triple layer approach

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5th International Conference on Semiconductor technology, ISTC 2006

作者： Lin, Yi Shih Chen, Chao Jung Hao, Michael Xing, GuoQiang Logic Technology Development Center Semiconductor Manufacturing International Corporation

ISBN: (纸本)1566774373

Via-first-trench-last (VFTL) has become a popular approach to dual damascene (DD) patterning. PR remaining and PR poison issue are getting worse beyond 65nm dual damascene patterning. Tri-layer approach can provide etch stop layer protection, excellent substrate reflectivity control, PR remaining gain and PR poison reduction. LTO (low temperature oxide) and via fill material also became a good candidate for 193 nm anti-reflection layer and hard mask for trench etching. Topics such as performance in spin coating, trench lithography, plasma etching, will be discussed.

关键词： Nanotechnology

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SAT-based methods for sequential hardware equivalence verification without synchronization

SAT-based methods for sequential hardware equivalence verifi...

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BMC'2003, First International Workshop on Bounded Model Checking

作者： Khasidashvili, Zurab Hanna, Ziyad Logic and Validation Technology Design Technology Division Intel Development Center Haifa Israel

The BDD- and SAT-based model checking and verification methods normally require an initial state. Here we are concerned with sequential hardware verification, where an initial state must be one of the reset states. In practice, a reset state is not always given by the designer, and computing a reset state of a circuit is a hard problem. In this paper we propose a method allowing usage of SAT-based verification methods without a need for a user-given or a computed initial state. The idea is to employ a binary encoding of 3-valued modeling of circuits, and use the undefined state X as a reset state. © 2003 Published by Elsevier Science B.V.

关键词： Synchronization

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Interfacial layer development for 20nm high-k last integration scheme

Interfacial layer development for 20nm high-k last integrati...

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作者： Gao, Hanjie Zhao, Jie Min, Jiahua Zeng, Yizhi Awut, Kurban Song, Woeiji Yu, Shaofeng School of Materials Science and Engineering Shanghai University China Logic Technology and Development Center SMIC China

ISBN: (纸本)9781607685395

With the characteristic dimension scaling down of CMOS device, the gate leakage increases significantly and the device gets low reliability performance. Then EOT (Equivalent Oxide Thickness) should be decreased, and more performance would be gained with leakage and reliability sacrifice by an optimized dielectric interfacial layer and high-k material. In this paper, the methods to form IL are the key point of EOT scaling down with gate leakage sacrifice and post replacement metal gate (RMG) treatment lead to work function improvement with hysteresis reduction beyond 20nm node of CMOS devices. Based on data analysis we want to get some optimized conditions to make this layer an enhancement in the research of HKMG logic product process development. © 2014 The Electrochemical Society.

关键词： CMOS integrated circuits

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Fabrication and characterization of 1.5fF/um2 high-performance low-cost metal-insulator-metal capacitor in 0.13um and below Cu BEOL technologies

Fabrication and characterization of 1.5fF/um2 high-performan...

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2004 7th International Conference on Solid-State and Integrated Circuits technology Proceedings, ICSICT 2004

作者： Chen, Z. Lin, K.M. Kuo, C.C. Lia, Y.F. Huang, J.C. Su, T.C. Wang, J.P. Liao, C.C. Han, Q.H. Bei, D.H. Ang, T.C. Jeng, M.C. Center of Logic Technology Development and Manufacturing Semiconductor Manufacturing International Corp. Shanghai 201203 China

The capacitance density of industrial low-cost Metal-Insulator-Metal (MIM) capacitor in Cu Back-End-of-Line (BEOL) technologies has been improved to 1.5 fF/um2. which is 50% higher than the current foundry standard of 1.0fF/um2 [1,3]. In this paper, we present a method to fabricate the high-density MIM with only one additional mask required on top of the standard logic baseline Cu BEOL technologies. This MIM capacitor's reliability, voltage and temperature coefficients, thermal stability, and mismatching performance have been proved to be fully qualified to meet foundry's requirements. Without applying novel material nor using extra offsetting process loop the proposed MIM capacitor has a very good performance-over-cost ratio, which is promising to be implemented in 0.1Sum and below Cu BEOL technologies © 2004 IEEE.

关键词： Capacitors

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Arsenic dimer (As2+) Lightly Doped Drain(LDD)implantation study for 20nm logic device development

Arsenic dimer (As2+) Lightly Doped Drain(LDD)implantation st...

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作者： Sun, Hao Li, Yong Zhang, Shuai Xie, Xinyun Cai, Gorge Zhou, Zuyuan Shi, Xuejie He, Yonggen Shi, Weimin Ju, Jianhua Chen, Larry Yu, Shaofeng School of Materials Science and Eng Shanghai University 200072 China Logic Technology and Development Center SMIC 201203 China

ISBN: (纸本)9781607685395

Process variation presents a significant challenge to future scaling of VLSI technology. Junction depth scaling with small Vth variation is required for the 45 nm technology node and beyond. Variations in MOSFET characteristics due to random dopant fluctuation (RDF) may become a fundamental limit to device scaling and circuit complexity. Arsenic dimer (As2+) implant has been used for the formation of ultra-shallow source drain extensions for NMOS transistors below 45nm, CMOS logic process. As Dimer requires only half the dose and twice the energy of equivalent As+ so it is more favorable for much lower energy (+ implantation. However, arsenic dimer implantation showed better Vth mismatch performance than conventional As+ implantation. © 2014 The Electrochemical Society.

关键词： Capacitance

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Stacking faults and stress memorization technique study for n-type MOSFET performance improvement in all last High-k Metal Gate process development

Stacking faults and stress memorization technique study for ...

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作者： Li, Yong Sun, Hao Ju, Jianhua Logic Technology and Development Center SMIC 201203 China School of Materials Science and Eng Shanghai University 200072 China

ISBN: (纸本)9781607685395

In this paper, the stacking faults, stress memorization technique (SMT) and their impacts on n-type MOSFET device performance were studied. SMT combines source/drain deep PAI improves short channel device electron mobility 25%, Ion/Ioff curve 8% and long channel device 10% and 4%, respectively. A mechanism why SMT improves device performance in all last HKMG (High-k Metal Gate) process was proposed. During SMT anneal, poly expands much more than the hard nitride cap, the thermal stress gain from poly transformation from an elastic state to a plastic state was transferred into the channel, the stress was then memorized by the source/drain stacking faults, that were formed during the SMT anneal at deep pre-amorphous source/drain area. After poly removal, the tensile stress still exists, as it was retained by the stacking faults. The stress intensity along channel, Sxx, is the key parameter to index the stress effect on device performance improvement;it is related to poly volume and gate length. And based on this, the reasons that long channel and short channel devices performance gain are much smaller than that of the middle channel devices were also discussed. © 2014 The Electrochemical Society.

关键词： Stacking faults

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Global Scaling Inductor Models with Temperature Effect

Global Scaling Inductor Models with Temperature Effect

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2008 9th International Conference on Solid-State and Integrated-Circuit technology

作者： Danmy He Jenhao Cheng Leo Chen Logic Technology Development Center SMIC

This paper presents global lumped-element circuit models of spiral inductor and differential inductor respectively considering quality factor dependence on *** resistance components in equivalent circuits of spiral inductor and differential inductor were adopted to reflect quality factor dependence on temperature in global *** the global models were shown to give excellent agreement with measured data for inductors of various dimension over temperature range from -40℃to 125℃,which will facilitate customers to design circuits for worst temperature conditions in real world applications.

关键词： Global Scaling Inductor Models with Temperature Effect

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