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检索条件"机构=Logic Technology Development Center"
67 条 记 录,以下是1-10 订阅
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Device Design Guidelines to Boost up AC Performance of CFET (Complementary Field-Effect-Transistor)-Based Inverter
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2025年
作者: Lim, Jaehyuk Han, Donghwan Sung, Juho Yoon, Seokchan Kang, Sanghyun Kim, Gwon Baac, Hyoung Won Shin, Changhwan Sungkyunkwan University Department of Electrical and Computer Engineering Suwon16419 Korea Republic of Korea University School of Electrical Engineering Seoul02841 Korea Republic of Samsung Electronics Semiconductor Research and Development Center Logic Technology Development Team Hwaseong18448 Korea Republic of
Complementary Field-Effect Transistors (CFETs) have emerged as promising candidates for next-generation semiconductor devices. CFETs feature a structure with an NMOS (or PMOS) transistor at the bottom and a transistor... 详细信息
来源: 评论
Dummy poly removal impact factors and improvement in HKMG last process
Dummy poly removal impact factors and improvement in HKMG la...
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作者: Zeng, Yizhi Zhao, Jie Gao, Hanjie Awuti, Kurban Song, Woeiji Yu, Shaofeng Zhang, Qin Lin, Yihui Liu, Jialei Liu, H.X. Logic Technology and Development Center SMIC 201312 China
For 20/16nm HK-last and MG-last process, Dummy poly is removed by Wet process. This paper studies the factors impacting the dummy poly removal process, and presents some models to explain the impacting factors. Implan... 详细信息
来源: 评论
A new failure mechanism of gate-grounded MOSFET ESD device in 90nm technology
A new failure mechanism of gate-grounded MOSFET ESD device i...
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IEEE Conference on Electron Devices and Solid-State Circuits
作者: Zhang, Li-Fei Liao, Chin-Chang Liu, Wei Wong, Waisum Logic Technology and Development Center Semiconductor Manufacture International Corp. China
A new triggering phenomenon was observed on gate-grounded nMOS (ggnMOS) ESD device in 90nm technology. The trigger voltage has been measured at the value as low as 6V. However, the low triggering voltage does not resu... 详细信息
来源: 评论
65nm dual damascene patterning with triple layer approach
65nm dual damascene patterning with triple layer approach
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5th International Conference on Semiconductor technology, ISTC 2006
作者: Lin, Yi Shih Chen, Chao Jung Hao, Michael Xing, GuoQiang Logic Technology Development Center Semiconductor Manufacturing International Corporation
Via-first-trench-last (VFTL) has become a popular approach to dual damascene (DD) patterning. PR remaining and PR poison issue are getting worse beyond 65nm dual damascene patterning. Tri-layer approach can provide et... 详细信息
来源: 评论
SAT-based methods for sequential hardware equivalence verification without synchronization
SAT-based methods for sequential hardware equivalence verifi...
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BMC'2003, First International Workshop on Bounded Model Checking
作者: Khasidashvili, Zurab Hanna, Ziyad Logic and Validation Technology Design Technology Division Intel Development Center Haifa Israel
The BDD- and SAT-based model checking and verification methods normally require an initial state. Here we are concerned with sequential hardware verification, where an initial state must be one of the reset states. In... 详细信息
来源: 评论
Interfacial layer development for 20nm high-k last integration scheme
Interfacial layer development for 20nm high-k last integrati...
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作者: Gao, Hanjie Zhao, Jie Min, Jiahua Zeng, Yizhi Awut, Kurban Song, Woeiji Yu, Shaofeng School of Materials Science and Engineering Shanghai University China Logic Technology and Development Center SMIC China
With the characteristic dimension scaling down of CMOS device, the gate leakage increases significantly and the device gets low reliability performance. Then EOT (Equivalent Oxide Thickness) should be decreased, and m... 详细信息
来源: 评论
Fabrication and characterization of 1.5fF/um2 high-performance low-cost metal-insulator-metal capacitor in 0.13um and below Cu BEOL technologies
Fabrication and characterization of 1.5fF/um2 high-performan...
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2004 7th International Conference on Solid-State and Integrated Circuits technology Proceedings, ICSICT 2004
作者: Chen, Z. Lin, K.M. Kuo, C.C. Lia, Y.F. Huang, J.C. Su, T.C. Wang, J.P. Liao, C.C. Han, Q.H. Bei, D.H. Ang, T.C. Jeng, M.C. Center of Logic Technology Development and Manufacturing Semiconductor Manufacturing International Corp. Shanghai 201203 China
The capacitance density of industrial low-cost Metal-Insulator-Metal (MIM) capacitor in Cu Back-End-of-Line (BEOL) technologies has been improved to 1.5 fF/um2. which is 50% higher than the current foundry standard of... 详细信息
来源: 评论
Arsenic dimer (As2+) Lightly Doped Drain(LDD)implantation study for 20nm logic device development
Arsenic dimer (As2+) Lightly Doped Drain(LDD)implantation st...
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作者: Sun, Hao Li, Yong Zhang, Shuai Xie, Xinyun Cai, Gorge Zhou, Zuyuan Shi, Xuejie He, Yonggen Shi, Weimin Ju, Jianhua Chen, Larry Yu, Shaofeng School of Materials Science and Eng Shanghai University 200072 China Logic Technology and Development Center SMIC 201203 China
Process variation presents a significant challenge to future scaling of VLSI technology. Junction depth scaling with small Vth variation is required for the 45 nm technology node and beyond. Variations in MOSFET chara... 详细信息
来源: 评论
Stacking faults and stress memorization technique study for n-type MOSFET performance improvement in all last High-k Metal Gate process development
Stacking faults and stress memorization technique study for ...
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作者: Li, Yong Sun, Hao Ju, Jianhua Logic Technology and Development Center SMIC 201203 China School of Materials Science and Eng Shanghai University 200072 China
In this paper, the stacking faults, stress memorization technique (SMT) and their impacts on n-type MOSFET device performance were studied. SMT combines source/drain deep PAI improves short channel device electron mob... 详细信息
来源: 评论
Global Scaling Inductor Models with Temperature Effect
Global Scaling Inductor Models with Temperature Effect
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2008 9th International Conference on Solid-State and Integrated-Circuit technology
作者: Danmy He Jenhao Cheng Leo Chen Logic Technology Development Center SMIC
This paper presents global lumped-element circuit models of spiral inductor and differential inductor respectively considering quality factor dependence on *** resistance components in equivalent circuits of spiral in... 详细信息
来源: 评论