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检索条件"机构=Logic Technology Development Center"
67 条 记 录,以下是31-40 订阅
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Global scaling inductor models with temperature effect
Global scaling inductor models with temperature effect
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International Conference on Solid-State and Integrated Circuit technology
作者: Danmy He Jenhao Cheng Leo Chen Logic Technology Development Center SMIC Shanghai China
This paper presents global lumped-element circuit models of spiral inductor and differential inductor respectively considering quality factor dependence on temperature. Metal resistance components in equivalent circui... 详细信息
来源: 评论
Dielectric recoveries on O2 plasma damaged organosilicate low-k dielectrics
Dielectric recoveries on O2 plasma damaged organosilicate lo...
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24th Session of the Advanced Metallization Conference 2007, AMC 2007
作者: Shi, Hualiang Bao, Junjing Liu, Junjun Huang, Huai Smith, Ryan Scott Zhao, Qiu Ho, Paul S. Goodner, Michael D. Moinpour, Mansour Kloster, Grant M. Laboratory for Interconnect and Packaging University of Texas at Austin Microelectronics Research Center Austin TX 78758 United States Logic Technology Development Intel Corporation Hillsboro OR 97124 United States
The O2 plasma damage of porous OSG films was investigated by examining the origin of the dielectric loss and using a CH4 plasma treatment for dielectric recovery. To study the dielectric loss, a combination of analyti... 详细信息
来源: 评论
Dielectric recovery of plasma damaged organosilicate low-k films
Dielectric recovery of plasma damaged organosilicate low-k f...
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2008 MRS Spring Meeting
作者: Shi, Hualiang Bao, Junjing Huang, Huai Liu, Junjun Smith, Ryan Scott Sun, Yangming Ho, Paul S. Mcswiney, Michael L. Moinpour, Mansour Kloster, Grant M Laboratory for Interconnect and Packaging Microelectronics Research Center University of Texas at Austin Pickle Research Campus Austin TX 78758 United States Logic Technology Development Intel Corporation Hillsboro OR 97124 United States
Methyl depletion and subsequent moisture uptake have been found to be the primary plasma damages leading to dielectric loss in porous organosilicate (OSG) low-k dielectrics. A vacuum vapor silylation process was devel... 详细信息
来源: 评论
Effect of CH4 plasma treatment on O2 plasma ashed organosilicate low-k dielectrics
Effect of CH4 plasma treatment on O2 plasma ashed organosili...
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2007 MRS Spring Meeting
作者: Shi, Hualiang Bao, Junjing Liu, Junjun Huang, Huai Ho, Paul S. Goodner, Michael D. Moinpour, Mansour Kloster, Grant M. Laboratory for Interconnect and Packaging Microelectronics Research Center University of Texas at Austin 10100 Burnet Road Austin TX 78758 United States Logic Technology Development Intel Corporation Hillsboro OR 97124 United States
During an O2 plasma ashing process, carbon depletion and subsequent moisture uptake caused an increase of keff and the leakage current in an organosilicate (OSG) low-k dielectric. For dielectric restoration, an additi... 详细信息
来源: 评论
Mechanistic Study of Plasma Damage and CH4 Recovery of Low k Dielectric Surface
Mechanistic Study of Plasma Damage and CH4 Recovery of Low k...
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IEEE International Conference on Interconnect technology
作者: J. J. Bao H. L. Shi J. J. Liu H. Huang P.S. Ho M. D. Goodner M. Moinpour G. M. Kloster Laboratory for Interconnect and Packaging Microelectronics Research Center University of Texas Austin Austin TX USA Logic Technology Development Intel Corporation Hillsboro OR USA
A mechanistic study was performed to investigate plasma damage and CFL, recovery of porous carbon-doped oxide (CDO) low k surfaces. First the nature of damage was examined for different plasma treatments in a standard... 详细信息
来源: 评论
65nm dual damascene patterning with triple layer approach
65nm dual damascene patterning with triple layer approach
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5th International Conference on Semiconductor technology, ISTC 2006
作者: Lin, Yi Shih Chen, Chao Jung Hao, Michael Xing, GuoQiang Logic Technology Development Center Semiconductor Manufacturing International Corporation
Via-first-trench-last (VFTL) has become a popular approach to dual damascene (DD) patterning. PR remaining and PR poison issue are getting worse beyond 65nm dual damascene patterning. Tri-layer approach can provide et... 详细信息
来源: 评论
New aspects of HCI test for ultra-short channel n-MOSFET devices
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Chinese Physics B 2006年 第11期15卷 2742-2745页
作者: 马晓华 郝跃 王剑屏 曹艳荣 陈海峰 Microelectronics Institute Xidian University Xi'an 710071 China Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices Xidian University Xi'an 710071 China Logic Technology Development Center SMIC Shanghai 201203 China
Hot carriers injection (HCI) tests for ultra-short channel n-MOSFET devices were studied. The experimental data of short channel devices (75-90 nm), which does not fit formal degradation power law well, will bring... 详细信息
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A new failure mechanism of gate-grounded MOSFET ESD device in 90nm technology
A new failure mechanism of gate-grounded MOSFET ESD device i...
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IEEE Conference on Electron Devices and Solid-State Circuits
作者: Zhang, Li-Fei Liao, Chin-Chang Liu, Wei Wong, Waisum Logic Technology and Development Center Semiconductor Manufacture International Corp. China
A new triggering phenomenon was observed on gate-grounded nMOS (ggnMOS) ESD device in 90nm technology. The trigger voltage has been measured at the value as low as 6V. However, the low triggering voltage does not resu... 详细信息
来源: 评论
Expression reduction systems and extensions: An overview
Lecture Notes in Computer Science (including subseries Lectu...
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Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 2005年 3838 LNCS卷 496-553页
作者: Dauert, John Kesner, Delia Khasidashvili, Zurab School of Computing Sciences University of East Anglia Norwich United Kingdom PPS CNRS Université Paris 7 France Logic and Validation Technology Design Technology Division Intel Development Center Haifa Israel
Expression Reduction Systems is a formalism for higherorder rewriting, extending Term Rewriting Systems and the lambdacalculus. Here we give an overview of results in the literature concerning ERSs. We review confluen... 详细信息
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A New Failure Mechanism of Gate-grounded MOSFET ESD Device in 9Onm technology
A New Failure Mechanism of Gate-grounded MOSFET ESD Device i...
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IEEE Conference on Electron Devices and Solid-State Circuits
作者: Li-Fei Zhang Chin-Chang Liao Wei Liu Waisum Wong Logic Technology and Development Center Semiconductor Manufacturing International Corporation China
A new triggering phenomenon was observed on gate-grounded nMOS (ggnMOS) ESD device in 90nm technology. The trigger voltage has been measured at the value as low as 6V. However, the low triggering voltage does not resu... 详细信息
来源: 评论