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28th IEEE Symposium on VLSI Circuits, VLSIC 2014

作者： Meterelliyoz, Mesut Al-Amoody, Fuad H. Arslan, Umut Hamzaoglu, Fatih Hood, Luke Lal, Manoj Miller, Jeffrey L. Ramasundar, Anand Soltman, Dan Wan, Ifar Wang, Yih Zhang, Kevin Logic Technology Development Intel Corporation Hillsboro OR United States Platform Engineering Group Intel Corporation Hillsboro OR United States

ISBN: (纸本)9781479933273

2nd generation 1Gbit 2GHz Embedded DRAM (eDRAM) with 4X lower self refresh power compared to prior generation is developed in 22nm Tri-Gate CMOS technology. Retention time has been improved by 3X (300us@95°C) by process and design optimizations. Source synchronous clocking is integrated in the design to reduce clock power without penalizing bandwidth. Charge pump power is reduced by 4X by employing comparator based regulation. Temperature controlled refresh enables minimum refresh power at all temperature conditions. © 2014 IEEE.

关键词： Clocks

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Grain Engineering Approaches for High-Performance Polysilicon Thin-Film Transistor Fabrication

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MRS Online Proceedings Library 2011年第1期508卷 55-65页

作者： G. K. Giust T. W. Sigmon Memory Technology & Integration LSI Logic Santa Clara USA Advanced Process and Development Group Lawrence Livermore National Laboratory Livermore USA

Using an approach we call “grain engineering,” we discuss several techniques to control grain growth during excimer laser annealing, to create low-defect density polysilicon films. By adjusting of laser parameters, for example, we obtain polysilicon films with grain sizes of more than 9 µm, without substrate heating. These high-quality films are used in the fabrication of low-temperature unhydrogenated polysilicon thin-film transistors (TFT’s) yielding mobilities of > 260 cm2/Vs and on/off current ratios > 107. We investigate the laser recrystallization of “prepatterned” films as another technique of grain engineering. We find the performance of TFT’s fabricated in active areas that are prepatterned before laser recrystallization is dramatically improved compared to those TFT’s fabricated from the laser recrystallization of blanket polysilicon films. A novel “recessed” structure is also examined as a new grain engineering tool. By depositing a blanket silicon film on a patterned oxide layer on a heat sink, the heat flow through the continuous silicon film may be controlled during laser recrystallization to simultaneously produce adjacent regions of remarkably different grain microstructure.

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Mechanical Stresses in Aluminum and Copper Interconnect Lines for 0.18µm logic Technologies

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MRS Online Proceedings Library (OPL) 2011年第1期563卷 189-189页

作者： Paul R. Besser Young-Chang Joo Delrose Winter Minh Van Ngo Richard Ortega Technology Development Group of Advanced Micro Devices Inc. One AMD Place Sunnyvale CA 94088. Current address: Motorola-AMD Alliance Logic Technology 3501 Ed Bluestein Blvd MD K-10 Austin TX 78721. #AMIA Laboratories (Advanced Materials Instruments and Analysis Inc.) 7801 North Lamar Suite C-73 Austin TX 78752

The mechanical stress state of conventional Al and damascene Cu lines of a 0.18 pm logic technology flow have been determined using a novel X-Ray diffraction method that permits measurement of stress on an array of critical-dimension lines on the product die. The effect of high density plasma oxide deposition and the influence of low-K dielectrics on the stress state of the Al lines is described. The effect of materials properties and fabrication methodology on the stress state of damascene Cu lines is shown with measurement of mechanical stress and strain in passivated lines at room temperature and during annealing. The effect of underlayer on the damascene Cu stress state is also quantified.

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Thermal sensor variation reduction in deep sub 100nm process technologies

Thermal sensor variation reduction in deep sub 100nm process...

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IEEE SENSORS

作者： David E. Duarte Mohamed Abdelmoneum Greg Taylor Logic Technology Development Intel Corporation Hillsboro OR USA Intel Architecture Group Intel Corporation Hillsboro OR USA Circuit Research Laboratory Intel Corporation Hillsboro OR USA

As technology scales, the impact of process variation to device and circuit performance has increased significantly. The presented statistical design approach illustrates the importance of pre-silicon circuit performance characterization under random variation stress. The measured data shows that by applying sound analog layout rules, actual variation can be reduced by 30% and that compensation techniques like chopping for amplifier offset cancellation and current source mismatch reduction are effective in lowering variation further by up to 55%. The choice between the static and dynamic application of these techniques is also discussed.

关键词： Temperature sensors Resistors Circuit optimization Temperature measurement Layout Encoding

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The high-k solution

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IEEE SPECTRUM 2007年第10期44卷 29-35页

作者： Bohr, Mark T. Chau, Robert S. Ghani, Tahir Mistry, Kaizad Process architecture and integration Intel Transistor Transistor technology and integration Logic and technology development group

The article reports on Intel's latest Core 2 microprocessors, also known as Penryn. This latest innovation from Intel is based on a 45-nanometer CMOS process technology. It is expected to run cooler and faster than previous microprocessors. The development of the Penryn was accomplished through a major breakthrough on the way the gate stack was manufactured. Intel developers experienced a shortage of atoms when the transistor's gate oxide reached a thickness of only 5 atoms. They developed the high-k plus metal gate transistors to address the limitations they faced with the silicon dioxide insulators. Penryn processors can have as much as 820 million transistors, versions of which can be used for different devices including mobile, desktop, server applications, and workstations.

关键词： MICROPROCESSORS TRANSISTORS SILICA METAL insulator semiconductors ATOMS NANOSTRUCTURED materials TECHNOlogicAL innovations COMPUTERS

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Range based model for technology requirements: Hybrid vehicle technology assessment case study

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International Journal of Automotive technology and Management 2007年第4期7卷 314-326页

作者： Jordan, Stephen W. Daim, Tugrul U. Department of Engineering and Technology Management Maseeh College of Engineering and Computer Science Portland State University P.O. Box 751 Portland OR 97207 United States Portland State University ETM Department Intel Corporation Logic Technology Development Group Department of Engineering Technology Management Maseeh College of Engineering and Computer Science Portland State University PSU

This paper presents a performance based technology assessment model. The model was used in a case study aimed at improving the performance (mpg) of a basic hybrid vehicle. The assessment model and case study included a gap analysis, a scouting report for candidate technologies, a technology evaluation and selection model, implementation recommendations, and a diffusion and adoption analysis. Hybrid vehicles are an emerging innovation in vehicle manufacturing that can potentially reduce the amount of carbon emissions associated with 'mainstream' vehicles. Copyright © 2007 Inderscience Enterprises Ltd.

关键词： Mathematical models

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On the Scalability of Redundancy based SER Mitigation Schemes

On the Scalability of Redundancy based SER Mitigation Scheme...

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IEEE International Conference on Integrated Circuit Design and technology (ICICDT)

作者： N. Seifert B. Gill V. Zia M. Zhang V. Ambrose Logic Technology Development Q & R Intel Corporation Hillsboro OR USA Architecture for Quality and Reliability Intel Corporation Hillsboro OR USA Enterprise Microprocessor Group Intel Corporation Hillsboro OR USA Mobility Group Intel Corporation Folsom CA USA Enterprise Microprocessor Group Intgel Corporation Hudson MA USA

A novel circuit-level simulation strategy to assess the impact of charge sharing on the upset rate of redundancy based radiation hardened designs is introduced. Accelerated measurements conducted at the Los Alamos National Laboratory show a 10s or better reliability of hardened latches over standard latches for 45nm and 90nm implementations. Despite this encouraging trend, our simulations project that compact redundancy hardened designs will have soft error rates similar to non-hardened designs within a few technology generations if no additional mitigation techniques are applied to reduce the impact of charge sharing.

关键词： Scalability Redundancy Circuit simulation Error analysis Radiation hardening Space technology Computational modeling Clocks Latches Random access memory

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A 2.2-$\mu\hbox{m}$-Pitch Single-Transistor Charge-Modulation Pixel in a 0.13-$\mu\hbox{m}$ CMOS Process

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IEEE Transactions on Electron Devices 2007年第10期54卷 2623-2629页

作者： Arnaud Tournier Guo-Neng Lu FranÇois Roy Benoit Deschamps Front-End Technology and Manufacturing Group Advanced Research and Development High Performance Logic and Derivatives Process Technology Development Innovative Solutions for CMOS Imaging STMicroelectronics Crolles France INL Laboratory Centre National de Recherche Scientifique (CNRS)-Ecole Centrale de Lyon-Institut National des Sciences Appliquées Institut des Nanotechnologies de Lyon Villeurbanne France INL Laboratory Institut des Nanotechnologies de Lyon Villeurbanne France STMicroelectronics Crolles France

This paper presents the investigation of a 2.2-mum-pitch single-transistor pixel designed in a 0.13-mum CMOS process. Based on charge-induced potential variation of the floating-body of the transistor, this single pixel device can be operated to perform photodetection, charge integration, signal readout, and reset. The main electrical characteristics of the pixel are evaluated by device modeling and simulations as well as measurements of test chips. With optimization of process and electrical parameters, testing results show a conversion factor of 47 muV/hole, a charge-handling capability of 3500 holes, a temporal noise of four holes, and a dynamic range of 40 dB.

关键词： Transistors Electric potential logic gates CMOS integrated circuits Capacitance Noise Semiconductor device measurement

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Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices

Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Dev...

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Annual International Symposium on Reliability Physics

作者： N. Seifert P. Slankard M. Kirsch B. Narasimham V. Zia C. Brookreson A. Vo S. Mitra B. Gill J. Maiz Logic Technology Development Q&R Intel Corporation Hillsboro OR USA Department of Electrical Engineering and Computer Science Vanderbilt University Nashville TN USA Enterprise Microprocessor Group Intel Corporation Hillsboro OR USA Digital Enterprise Group Q&R Intel Corporation Hillsboro OR USA Logic Technology Development Q&R Intel Corporation Folsom CA USA Department of Electrical Engineering University of Stanford Stanford CA USA

This work provides a comprehensive summary of radiation-induced soft error rate (SER) scaling trends of key CMOS bulk devices. Specifically we analyzed the SER per bit scaling trends of SRAMs, sequentials and static combinational logic. Our results show that for SRAMs the single-bit soft error rate continues to decrease whereas the multi-bit SER increases dramatically. While the total soft error rate of logic devices (sequentials and static combinational devices) has not changed significantly, a substantial increase in the susceptibility to alpha particles is observed. Finally, a novel methodology to extract one-dimensional cross sections of the collected charge distributions from measured multi-bit statistics is introduced

关键词： Error analysis logic devices Random access memory Neutrons Testing Interleaved codes CMOS logic circuits CMOS technology Microprocessors Alpha particles

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Enhancing microprocessor immunity to power supply noise with clock/data compensation

Enhancing microprocessor immunity to power supply noise with...

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2005 Symposium on VLSI Circuits

作者： Rahal-Arabi, Tawfik Taylor, Greg Barkatullah, Javed Wong, Keng L. Ma, Matthew Logic Technology Development Desktop Platforms Group Intel Corporation

ISBN: (纸本)490078401X

This paper demonstrates an alternative to the conventional wisdom that microprocessors require a flat impedance spectrum across a broad range of frequencies in order to deliver maximum operating frequency. Delivering this impedance requires large amounts of on-die capacitance. We show that proper co-design of the clock and power distribution networks can relax this requirement, saving the area and leakage power needed for on-die decoupling. Measurements made on a 130 nm processor demonstrate the approach.

关键词： Microprocessor chips

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