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Symposium on VLSI Circuits

作者： T. Rahal-Arabi G. Taylor J. Barkatullah K.L. Wong M. Ma Logic Technology Development / Desktop Platforms Group Intel Corporation USA

This paper demonstrates an alternative to the conventional wisdom that microprocessors require a flat impedance spectrum across a broad range of frequencies in order to deliver maximum operating frequency. Delivering this impedance requires large amounts of on-die capacitance. We show that proper co-design of the clock and power distribution networks can relax this requirement, saving the area and leakage power needed for on-die decoupling. Measurements made on a 130 nm processor demonstrate the approach.

关键词： Microprocessors Power supplies Clocks Impedance Frequency Circuit noise Capacitance Voltage Electricity supply industry logic

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Reducing the impact of power supply noise on microprocessor performance

Reducing the impact of power supply noise on microprocessor ...

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14th Topical Meeting on Electrical Performance of Electronic Packaging 2005

作者： Rahal-Arabi, Tawfik Wong, Keng L. Ma, Matthew Barkatullah, Javed Taylor, Greg Mobile Platform Architecture Development Intel Corporation 15400 NW Greenbrier Pkwy. Beaverton OR 97006 Logic Technology Development Intel Corporation Mobile Platform Architecture Development 15400 NW Greenbrier Pkwy. Beaverton OR 97006 Desktop Products Group Intel Corporation Mobile Platform Architecture Development 15400 NW Greenbrier Pkwy. Beaverton OR 97006

ISBN: (纸本)0780392205

In this paper we demonstrate that it is possible to design circuits insensitive to power supply noise at frequencies in the range of 200 MHz to 500 MHz. We show that by using proper filter design at the beginning of the clock distribution network we increase the clock to data tracking and mitigate the impact of power supply noise on maximum operating frequency. We prove the theory with measurements using a 130 nm processor as an experimental validation vehicle. © 2005 IEEE.

关键词： Microprocessor chips

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Single stress liner for both NMOS and PMOS current enhancement by a novel ultimate Spacer process

Single stress liner for both NMOS and PMOS current enhanceme...

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IEEE International Electron Devices Meeting

作者： Liu, YC Pan, JW Chang, TY Liu, PW Lan, BC Tung, CH Tsai, CH Chen, TF Lee, CJ Wang, WM Chen, YA Shih, HL Tung, LY Cheng, LW Shen, TM Chiang, SC Lu, MF Chang, WT Luo, YH Nayak, D Gitlin, D Meng, HL Tsai, CT United Microelectronics Corporation (UMC) Central R and D Exploratory Technologies Division Hsin-Chu Science Park 30077 No. 3 Li-Hsin Rd. II Taiwan Xilinx Foundry Group CMOS Technology Development San Jose CA 95124 2100 Logic Drive United States

ISBN: (纸本)078039268X

For the first time, 15% and 7% drive current improvement is simultaneously achieved in both N/PMOS by adopting ultimate spacer process (USP) with a single stress liner. High out-of-plane stress in the channel accounts for the simultaneously enhanced drive current in N/PMOS. A 15% speed enhancement without compromising yield and product qualification in Field-Programmable Gate Arrays (FPGA) confirms immediate manufacturing feasibility of USP. This process provides a unique approach to significantly enhance device performance for 65nm CMOS technology and beyond. Extreme current increase of 25% in NMOS and 35% in PMOS can be achieved by applying additional strain enhancement methods.

关键词： MOS devices

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Reducing the impact of power supply noise on microprocessor performance

Reducing the impact of power supply noise on microprocessor ...

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IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEPS)

作者： T. Rahal-Arabi K.L. Wong M. Ma J. Barkatullah G. Taylor Mobile Platform Architecture Development Mobile Platform Architecture Development Intel Corporation Beaverton OR USA Logic Technology Development Mobile Platform Architecture Development Intel Corporation Beaverton OR USA Desktop Products Group Mobile Platform Architecture Development Intel Corporation Beaverton OR USA

In this paper, we demonstrate that it is possible to design circuits insensitive to power supply noise at frequencies in the range of 200 MHz to 500 MHz. We show that by using proper filter design at the beginning of the clock distribution network we increase the clock to data tracking and mitigate the impact of power supply noise on maximum operating frequency. We prove the theory with measurements using a 130 nm processor as an experimental validation vehicle.

关键词： Power supplies Noise reduction Microprocessors Frequency Delay lines Clocks Low-frequency noise Impedance Phase modulation Circuit noise

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A novel approach for the patterning and high-volume production of Sub-40-nm gates

A novel approach for the patterning and high-volume producti...

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作者： Romero, Karla Stephan, Rolf Grasshoff, Gunter Mazur, Martin Ruelke, Hartmut Huy, Katja Klais, Jochen McGowan, Sarah Dakshina-Murthy, Srikanteswara Bell, Scott Wright, Marilyn Fab36 01109 Dresden Germany Saxony 01109 Dresden Germany Sunnyvale CA 94088 United States Singapore 469032 Singapore 300 mm Fab36 Dresden Germany Fab36 Dresden Germany Fab36 Dresden Germany FEOL Etch Process Engineering Group FEOL Process Development 300-mm Facility Dresden Germany CVD and PVD Projects AMD's FAB30 Thin Films Group FAB30 Saxony Dresden Germany Defect Yield Enhancement Group in Fab30 Department Sunnyvale CA AMD Singapore Advanced Process Development Group Sunnyvale CA Logic Technology Development AMD's Sunnyvale CA

A novel approach for the patterning and manufacturing of sub-40-nm gate structures is presented. Rather than using resist or an inorganic hardmask as the patterning layer, this gate patterning scheme uses an amorphous carbon (a:C) and cap hardmask to pattern small gates. Healthy and manufacturable gate lengths have been achieved below 35 nm with this scheme, and the potential exists for further extendibility. © 2005 IEEE.

关键词： Gates (transistor)

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Fundamentals of Cu/Barrier-Layer Adhesion in Microelectronic Processing

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MRS Online Proceedings Library 2005年第1期863卷 B9.2-1-B9.2-6页

作者： Harsono Simka Sadasivan Shankar Carolyn Duran Michael Haverty Technology CAD Department Logic Technology Development USA Storage Technologies Group Technology and Manufacturing Group Intel Corporation Santa Clara USA

Copper is most widely used interconnect material in present silicon microelectronic technologies. As such, multiple interfaces formed by a thin Cu layer and other materials must be engineered to achieve the desired chemical, mechanical, and electrical properties. Adhesion between Cu and the barrier layer, as well as between Cu and the dielectric, is of particular interest, due to its role in controlling interfacial stability and Cu electromigration behavior [1]. This work focuses on understanding how the interface chemistry affects adhesion. Firstprinciples density functional theory (DFT) calculations were used to determine chemical adhesion energies of interfaces formed by Cu and various metals considered as a diffusion barrier, including Ta, TiN, and W. Calculations predicted increasing adhesion strength in the order of TiN < Si-doped TiN < TaN < Ta, consistent with wetting experiments done using 100Å thick Cu layer samples. The effects of doping at the interface using light elements (C, N, O) were also determined. Calculations were also done for interfaces of Cu with two different classes of amorphous dielectric materials, i.e. silicon nitride and silicon carbide, for which detailed material characterizations are often difficult and time consuming. Calculations predicted Cu/Si-nitride and Cu/Si-carbide adhesion strengths consistent with 4-pt-bend experiments, including the improvement in adhesion energies when silicon was used to dope the interface. In addition, weaker interfaces provide low-resistance diffusion paths for Cu atoms during electromigration. The first-principles based modeling, validated by select adhesion measurements, provides a predictive approach to effectively determine adhesion strengths and predict electromigration reliability in interconnects.

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History-effect-conscious SPICE model extraction for PD-SOI technology

History-effect-conscious SPICE model extraction for PD-SOI t...

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2004 IEEE International SOI Conference, Proceedings

作者： Goo, Jung-Suk An, Judy Xilin Thuruthiyil, Ciby Ly, Tran Chen, Qiang Radwin, Martin Wu, Zhi-Yuan Lee, Michael S.L. Zamudio, Luis Yonemura, James Assad, Farzin Pelella, Mario M. Icel, Ali B. Logic Technology Development Group Advanced Micro Devices Sunnyvale CA 94088-3453

The explicit fitting guidelines for AC and DC characteristics specifically focussed on accurate modeling of the history effects in PD-SOI-CMOS circuits were discussed. The measured data showed a saturated slope in the negative-bias range and it was an artifact of high resistance and partial depletion of the thin-body. The VDD dependence of the history-effect were different since the log-scale slope of the dashed-line was 45% higher than that of the solid-line in the low-bias forward region. Analysis shows that the fitting strategy raised the level of the history-effect by about 5% and also enhanced the voltage dependence.

关键词： Electric network analysis

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development and validation of an electromagnetic distributed power grid model for the 90nm Pentium/spl reg/ 4 processor

Development and validation of an electromagnetic distributed...

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Symposium on VLSI Circuits

作者： T. Rahal-Arabi Gang Ji M. Ma A. Muhtaroglu G. Taylor Logic Technology Development Microprocessor Design Group Intel Corporation Hillsboro OR USA

In this paper, we show that it is necessary to include the distributed effects of the power grid to accurately model the power supply noise for high frequency microprocessors. We show that high frequency resonances can be entirely missed if such effects are not modeled. Finally we prove the theory with experimental validation on the 90 nm Pentium/spl reg/ 4 microprocessor.

关键词： Power grids Electromagnetic modeling Inductance Frequency Capacitance Microprocessors Integrated circuit interconnections Predictive models Electric resistance Packaging

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History-effect-conscious SPICE model extraction for PD-SOI technology

History-effect-conscious SPICE model extraction for PD-SOI t...

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IEEE SOI-3D-Subthreshold Microelectronics technology Unified Conference (S3S)

作者： J.-S. Goo J.X. An C. Thuruthiyil T. Ly Q. Chen M. Radwin Zhi-Yuan Wu M.S.L. Lee L. Zamudio J. Yonemura F. Assad M.M. Pelella A.B. Icel Logic Technology Development Group Advanced Micro Devices Inc. Sunnyvale CA USA

This work presents explicit fitting guidelines for AC and DC characteristics, specifically focused on accurate modeling of the history effects in the PD-SOI CMOS circuits. The body potential of the PD-SOI device is primarily determined by the diode current, gate-body current, impact ionization current, junction capacitance, and gate-body capacitance. This paper also discusses artifacts associated with the parasitic currents and highly-resistive thin-body of the PD-SOI.

关键词： SPICE Switches MOS devices Propagation delay MOSFETs Diodes Switching circuits Voltage Capacitance logic devices

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A robust numerical pole-extraction algorithm for stratified medium

A robust numerical pole-extraction algorithm for stratified ...

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IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEPS)

作者： Y.C. Pan W.C. Chew Logic Technology Development Microprocessor Design Group Intel Corporation Hillsboro OR USA Computational Electromagnetics Department of Electrical and Computer Engineering University of Illinois Urbana-Champaign IL USA

Recent advances in VLSI technology heighten the need to accurately characterize three-dimensional (3D) complex interconnect structures embedded in a layered dielectric medium. Fast evaluation of the multilayer Green's function is often the key in developing an integral equation based algorithm to tackle this problem. Some of the existing pole extraction algorithms are geometry dependent. In This work we present a refined pole extraction algorithms that was conceived for finding poles in a general stratified medium at an arbitrary frequency.

关键词： Robustness Integral equations logic design Microprocessors Computational electromagnetics Very large scale integration Dielectrics Nonhomogeneous media Green function Frequency

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