An efficient, static fast multipole method (FMM) based algorithm is presented in this paper for the evaluation of the parasitic capacitance of 3-D microstrip signal lines embedded in stratified dielectric media. The e...
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An efficient, static fast multipole method (FMM) based algorithm is presented in this paper for the evaluation of the parasitic capacitance of 3-D microstrip signal lines embedded in stratified dielectric media. The effect of dielectric interfaces on the capacitance matrix is included in the stage of FMM when outgoing multipole expansions are used to form local multipole expansions. The algorithm retains O(N) computational and memory complexity of the free-space FMM, where N is the number of conductor patches.
An enhanced thermal management mechanism that reduces power by scaling frequency and voltage in response to excessive temperatures is presented. The voltage transition process is done transparently to the execution of...
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An enhanced thermal management mechanism that reduces power by scaling frequency and voltage in response to excessive temperatures is presented. The voltage transition process is done transparently to the execution of applications. The enhanced mechanism achieves an /spl sim/50% power reduction while limiting the performance impact to only /spl sim/20% for the duration of the thermal event. The approach allows the processor to meet its performance and reliability goals without additional thermal solution costs.
The mechanical stress state of damascene-fabricated Al interconnect lines was determined on an array of lines on the product die of a logictechnology device. Narrow, unpassivated, damascene Al lines have a purely hyd...
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The mechanical stress state of damascene-fabricated Al interconnect lines was determined on an array of lines on the product die of a logictechnology device. Narrow, unpassivated, damascene Al lines have a purely hydrostatic stress (108 MPa). The hydrostatic stress of damascene Al lines (411 MPa) is much larger once the dielectric is deposited. However, the maximum shear stress remains small in magnitude, compared to RIE Al lines of similar thermal history and aspect ratio. The stress of damascene lines was measured as a function of linewidth. Unpassivated, wide lines, have compressive stresses along the length and width and zero along the line height. Passivated wide lines have a biaxial, tensile stress in-plane and zero along the line height.
The mechanical stress state of conventional Al, damascene Al and damascene Cu lines of a 0.18 μm logictechnology flow has been determined using a novel X-Ray diffraction method that permits measurement of stress on ...
The mechanical stress state of conventional Al, damascene Al and damascene Cu lines of a 0.18 μm logictechnology flow has been determined using a novel X-Ray diffraction method that permits measurement of stress on an array of critical-dimension lines on the product die. The mechanical stress levels in narrow RIE Al lines are small when the lines are unpassivated, but quite large (Hydrostatic stress of 537 MPa) when an inter-level dielectric (ILD) is deposited onto the lines. The large stress level is an important reliability concern for the IC industry. The damascene fabrication methodology changes the magnitude and distribution of stress in the Al interconnect lines. Unpassivated, damascene Al lines have a purely hydrostatic stress. Even though the deposition temperature of the metal and ILD are the same for RIE and damascene. Al lines, the hydrostatic stress of passivated, damascene Al lines (411 MPa) and the maximum shear stress in the lines are sharply reduced. Comparing damascene Al and Cu lines, it is found that the stresses are much smaller in Cu than Al (Hydrostatic stress of 286 MPa), suggesting that stress-induced voiding may be less of a reliability concern for Cu.
This paper investigate the impact of CMOS (complementary metal-oxide-semiconductor) gate microstructure on the reliability and performance of deep-submicrometer CMOS transistors. The amorphous silicon (/spl alpha/-Si)...
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This paper investigate the impact of CMOS (complementary metal-oxide-semiconductor) gate microstructure on the reliability and performance of deep-submicrometer CMOS transistors. The amorphous silicon (/spl alpha/-Si) gate provides better capability for suppression of boron penetration in p/sup +/ doped gate p-channel MOSFETs, but gate depletion in the /spl alpha/-Si gate is slightly more severe than that of the poly-Si gate. The gate-length-dependent gate-depletion effect, in which the difference in linear g/sub m/ between MOSFETs with two different gate microstructures shows a strong L/sub g/-dependence, is reported and interpreted by impurity diffusion along the grain boundary. A gate nitrogen implant as an effective method for suppression of the boron diffusion is also discussed with emphasis on the impact on both device reliability and performance.
The size distribution of aluminum oxide droplets and particles in rocket exhausts is needed for the prediction of two-phase motor performance losses and plume radiative heating. Current estimates of size are based upo...
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Microwave probes are used extensively for linear and nonlinear characterization of microwave devices on wafer and are commercially available for use at frequencies up to 65 GHz. An on-wafer noise measurement test syst...
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Microwave probes are used extensively for linear and nonlinear characterization of microwave devices on wafer and are commercially available for use at frequencies up to 65 GHz. An on-wafer noise measurement test system, for discrete devices, is now commercially available and on-wafer power measurement techniques are emerging slowly. These probes are also getting more recognition for the testing of packaged chips, packages, and modules. More accurate calibration techniques and their on-wafer validation are being developed. Automatic testing of MMIC wafers, using an integrated test system, is a key requirement for the development of low-cost IC production.
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