咨询与建议

限定检索结果

文献类型

  • 26 篇 会议
  • 1 篇 期刊文献

馆藏范围

  • 27 篇 电子文献
  • 0 种 纸本馆藏

日期分布

学科分类号

  • 5 篇 理学
    • 3 篇 物理学
    • 1 篇 化学
    • 1 篇 海洋科学
    • 1 篇 生物学
    • 1 篇 系统科学
  • 4 篇 工学
    • 3 篇 电子科学与技术(可...
    • 2 篇 计算机科学与技术...
    • 1 篇 电气工程
    • 1 篇 信息与通信工程
    • 1 篇 化学工程与技术
    • 1 篇 生物医学工程(可授...
    • 1 篇 软件工程
    • 1 篇 生物工程

主题

  • 9 篇 mos devices
  • 8 篇 degradation
  • 7 篇 stress
  • 6 篇 random access me...
  • 5 篇 high k dielectri...
  • 4 篇 threshold voltag...
  • 4 篇 high-k gate diel...
  • 4 篇 titanium compoun...
  • 4 篇 neutrons
  • 4 篇 niobium compound...
  • 4 篇 error analysis
  • 4 篇 cmos technology
  • 3 篇 circuit simulati...
  • 3 篇 electron traps
  • 3 篇 logic devices
  • 3 篇 electric breakdo...
  • 2 篇 voltage
  • 2 篇 transistors
  • 2 篇 semiconductor de...
  • 2 篇 dielectrics

机构

  • 6 篇 logic technology...
  • 5 篇 technology devel...
  • 3 篇 portland technol...
  • 3 篇 portland technol...
  • 2 篇 intel corporatio...
  • 2 篇 department of el...
  • 2 篇 microelectronics...
  • 2 篇 enterprise micro...
  • 2 篇 architecture for...
  • 2 篇 department of el...
  • 2 篇 logic technology...
  • 1 篇 intel communicat...
  • 1 篇 smart power tech...
  • 1 篇 department of co...
  • 1 篇 intel corporatio...
  • 1 篇 fsm q&r
  • 1 篇 logic td q&r int...
  • 1 篇 product reliabil...
  • 1 篇 logic technology...
  • 1 篇 design and techn...

作者

  • 10 篇 s. pae
  • 9 篇 m. agostinelli
  • 6 篇 c. prasad
  • 5 篇 n. seifert
  • 4 篇 s. ramey
  • 4 篇 j. maiz
  • 4 篇 j. hicks
  • 4 篇 b. gill
  • 3 篇 s. lau
  • 3 篇 k. mistry
  • 3 篇 s. jacobs
  • 2 篇 w. yang
  • 2 篇 v. ambrose
  • 2 篇 j. xu
  • 2 篇 norbert seifert
  • 2 篇 j. jopling
  • 2 篇 j. thomas
  • 2 篇 m. hattendorf
  • 2 篇 t. ghani
  • 2 篇 m. jones

语言

  • 27 篇 英文
检索条件"机构=Logic Technology Development Q&R"
27 条 记 录,以下是1-10 订阅
排序:
Characterization and Modeling of High Voltage MOS robustness During recirculation in Smart Power technologies
Characterization and Modeling of High Voltage MOS Robustness...
收藏 引用
European Conference on Solid-State Device research (ESSDErC)
作者: Michele Basso Marco Sambi Andrea Marcovati Smart Power Technology Development STMicrolectronics Milan Italy Automotive Q&R Failure Analysis STMicrolectronics Milan Italy
Smart Power IC can be subjected to high recirculation current through body-drain diodes of High Voltage MOS when the output circuitry is facing an inductive load. Within the new generations of technologies, the switch...
来源: 评论
On the Correlation of Laser-induced and High-Energy Proton Beam-induced Single Event Latchup
On the Correlation of Laser-induced and High-Energy Proton B...
收藏 引用
Annual International Symposium on reliability Physics
作者: Bahar Ajdari Samwel Sekwao ricardo Ascazubi Adam Neale Norbert Seifert Product Reliability Services Corporate Quality Network Intel Corporation Hillsboro OR Logic Technology Development Q&R Corporate Quality Network Intel Corporation Hillsboro OR 97124
We report on pulsed laser and high-energy proton induced Single Event Latchup (SEL) testing. Arrayed Silicon Controlled rectifier (SCr) structures that implement various different layout design styles relevant to SEL ...
来源: 评论
Assessment of fracture and elastoplastic properties of thin and very thin films
收藏 引用
AIP Conference Proceedings 2014年 第1期1601卷 158-167页
作者: M. Trueba D. Gonzalez I. Ocaña M. r. Elizalde J. M. Martinez-Esnaola M. T. Hernandez M. Haverty G. Xu D. Pantuso CEIT and TECNUN (University of Navarra) Manuel Lardizabal 15 20018 San Sebastián Spain Design Technology Solutions Intel Corporation Hillsboro 97124 (OR) USA Logic Technology Q&R Intel Corporation Hillsboro 97124 (OR) USA
Microelectronic industry is driven by the continuous miniaturization process conducing to the introduction of new materials. These materials are subjected to stresses mainly due to thermal mismatch, microstructural ch...
来源: 评论
Correlating low energy neutron SEr with broad beam neutron and 200 MeV proton SEr for 22nm CMOS Tri-Gate devices
Correlating low energy neutron SER with broad beam neutron a...
收藏 引用
Annual International Symposium on reliability Physics
作者: Shah Jahinuzzaman Balkaran Gill Vinod Ambrose Norbert Seifert Logic Technology Development Q&R Intel Corporation Hillsboro OR USA Intel Corporation Santa Clara CA USA
For terrestrial single event upset (SEU) characterization, JEDEC JESD89A requires using either broad beam neutron sources or at least four single neutron/proton particle energy sources. While computing ambient upset r... 详细信息
来源: 评论
Gate dielectric TDDB characterizations of advanced High-k and metal-gate CMOS logic transistor technology
Gate dielectric TDDB characterizations of advanced High-k an...
收藏 引用
Annual International Symposium on reliability Physics
作者: S. Pae C. Prasad S. ramey J. Thomas A. rahman r. Lu J. Hicks S. Batzer q. Zhao J. Hatfield M. Liu C. Parker B. Woolery Intel Corporation LTD Q&R ICF Q&R Portland Technology Development Hillsboro OR
Transition into High-K (HK) dielectric and Metal-Gate (MG) in advanced logic process has enabled continued technology scaling in support of Moore's law [1-2]. With this, CMOS operating fields have been increasing ... 详细信息
来源: 评论
reliability characterization of 32nm high-K and Metal-Gate logic transistor technology
Reliability characterization of 32nm high-K and Metal-Gate l...
收藏 引用
Annual International Symposium on reliability Physics
作者: Sangwoo Pae Ashwin Ashok Jingyoo Choi Tahir Ghani Jun He Seok-hee Lee Karen Lemay Mark Liu ryan Lu Paul Packan Chris Parker richard Purser Anthony St. Amour Bruce Woolery Q&R Intel Corporation Limited Hillsboro OR USA DID Manufacturing Hillsboro OR USA Hillsboro OR USA Portland Technology Development Hillsboro OR USA
High-K (HK) and Metal-Gate (MG) transistor reliability is very challenging both from the standpoint of introduction of new materials and requirement of higher field of operation for higher performance. In this paper, ... 详细信息
来源: 评论
Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology
Characterization of SILC and its end-of-life reliability ass...
收藏 引用
Annual International Symposium on reliability Physics
作者: S. Pae T. Ghani M. Hattendorf J. Hicks J. Jopling J. Maiz K. Mistry J. O'Donnell C. Prasad J. Wiedemer J. Xu Logic Technology Development Q&R Intel Corporation Hillsboro OR USA Portland Technology Development Hillsboro OR Intel Corporation Logic Technology Development Q&R Hillsboro USA Intel Corporation Logic Technology Development Q&R
Stress induced leakage current (SILC) has been observed on non-optimized high-K (HK) and metal-gate (MG) transistors. Large NMOS PBTI degradation and correlation to SILC increase on such gate stack is a result of larg... 详细信息
来源: 评论
BTI reliability of 45 nm high-K + metal-gate process technology
BTI reliability of 45 nm high-K + metal-gate process technol...
收藏 引用
Annual International Symposium on reliability Physics
作者: S. Pae M. Agostinelli M. Brazier r. Chau G. Dewey T. Ghani M. Hattendorf J. Hicks J. Kavalieros K. Kuhn M. Kuhn J. Maiz M. Metz K. Mistry C. Prasad S. ramey A. roskowski J. Sandford C. Thomas J. Thomas C. Wiegand J. Wiedemer Logic Technology Development Q&R USA PTD USA Intel Corporation Hillsboro OR USA
In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized HK film stack in ... 详细信息
来源: 评论
Multi-cell upset probabilities of 45nm high-k + metal gate SrAM devices in terrestrial and space environments
Multi-cell upset probabilities of 45nm high-k + metal gate S...
收藏 引用
Annual International Symposium on reliability Physics
作者: N. Seifert B. Gill K. Foley P. relangi Logic Technology Development Q&R Intel Corporation Hillsboro OR USA Architecture for Quality and Reliability Intel Corporation Hillsboro OR USA Design and Technology Solutions Intel Corporation Hillsboro OR USA Department of Electrical Engineering University of Stanford Stanford CA USA
Multi-cell soft errors are a key reliability concern for advanced memory devices. We have investigated single-bit (SBU) and multi-cell upset (MCU) rates of SrAM devices built in a 45 nm high-k + metal gate (HK+MG) tec... 详细信息
来源: 评论
Multi-cell upset probabilities of 45nm high-k + metal gate SrAM devices in terrestrial and space environments
Multi-cell upset probabilities of 45nm high-k + metal gate S...
收藏 引用
46th Annual 2008 IEEE International reliability Physics Symposium, IrPS
作者: Seifert, N. Gill, B. Foley, K. relangi, P. Logic Technology Development Q and R Intel Corporation Hillsboro OR 97124 United States Architecture for Quality and Reliability Intel Corporation Hillsboro OR 97124 United States Design and Technology Solutions Intel Corporation Hillsboro OR 97124 United States Stanford University Dept. of Electrical Engineering Stanford CA 94305 United States
Multi-cell soft errors are a key reliability concern for advanced memory devices. We have investigated single-bit (SBU) and multi-cell upset (MCU) rates of SrAM devices built in a 45nm high-k + metal gate (HK+MG) tech... 详细信息
来源: 评论