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European Conference on Solid-State Device research (ESSDErC)

作者： Michele Basso Marco Sambi Andrea Marcovati Smart Power Technology Development STMicrolectronics Milan Italy Automotive Q&R Failure Analysis STMicrolectronics Milan Italy

Smart Power IC can be subjected to high recirculation current through body-drain diodes of High Voltage MOS when the output circuitry is facing an inductive load. Within the new generations of technologies, the switching frequency increases to boost product efficiency, but this may trigger new failure mechanisms, in addition to the well-known efficiency loss due to intrinsic diodes conduction. The purpose of this work is to characterize a potentially harmful effect: the trigger of the parasitic bipolar transistor of the low side power MOS, when it is forced to turn-off abruptly during diode forward conduction. This phenomenon will be studied both theoretically and experimentally with the help of TCAD simulations and direct measurements, highlighting the importance of the substrate in this failure mechanism. Moreover, the impact of the component architecture together with the peculiar effects due to the bias of Low Side Drivers are investigated. Few layout variations improving the device robustness are shown, characterized, and discussed.

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On the Correlation of Laser-induced and High-Energy Proton Beam-induced Single Event Latchup

On the Correlation of Laser-induced and High-Energy Proton B...

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Annual International Symposium on reliability Physics

作者： Bahar Ajdari Samwel Sekwao ricardo Ascazubi Adam Neale Norbert Seifert Product Reliability Services Corporate Quality Network Intel Corporation Hillsboro OR Logic Technology Development Q&R Corporate Quality Network Intel Corporation Hillsboro OR 97124

ISBN: (数字)9781728131993

ISBN: (纸本)9781728132006

We report on pulsed laser and high-energy proton induced Single Event Latchup (SEL) testing. Arrayed Silicon Controlled rectifier (SCr) structures that implement various different layout design styles relevant to SEL have been designed and fabricated to make them accessible to both laser and beam testing. Our results demonstrate a qualitative but not quantitative correlation of laser- and beam-induced SEL threshold voltages and cross sections. Therefore, for a complete understanding of SEL sensitivities, pulsed laser injection remains a complementary technique.

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Assessment of fracture and elastoplastic properties of thin and very thin films

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AIP Conference Proceedings 2014年第1期1601卷 158-167页

作者： M. Trueba D. Gonzalez I. Ocaña M. r. Elizalde J. M. Martinez-Esnaola M. T. Hernandez M. Haverty G. Xu D. Pantuso CEIT and TECNUN (University of Navarra) Manuel Lardizabal 15 20018 San Sebastián Spain Design Technology Solutions Intel Corporation Hillsboro 97124 (OR) USA Logic Technology Q&R Intel Corporation Hillsboro 97124 (OR) USA

Microelectronic industry is driven by the continuous miniaturization process conducing to the introduction of new materials. These materials are subjected to stresses mainly due to thermal mismatch, microstructural changes or process integration which can be in the origin of mechanical reliability issues. To study these phenomena and even electromigration a good mechanical characterization of the materials is needed. This work aims at developing tests to assess fracture or elastoplastic behavior of thin and very thin metallic and polymeric films. The tests developed are based on indentation combined with sample preparation using mostly FIB. Among other techniques, different test geometries for microbeams have been evaluated and quantitative data have been obtained combining experimental results with analytical or numerical models, depending on the material under study. For the particular case of Cu cantilevers, a strong dependence of their plastic behavior on the orientation of the grains close to the fixed end has been detected. Grain orientation has been measured by EBSD and the plastic behavior has been modeled by FEM using an in-house crystal plasticity subroutine.

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Correlating low energy neutron SEr with broad beam neutron and 200 MeV proton SEr for 22nm CMOS Tri-Gate devices

Correlating low energy neutron SER with broad beam neutron a...

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Annual International Symposium on reliability Physics

作者： Shah Jahinuzzaman Balkaran Gill Vinod Ambrose Norbert Seifert Logic Technology Development Q&R Intel Corporation Hillsboro OR USA Intel Corporation Santa Clara CA USA

For terrestrial single event upset (SEU) characterization, JEDEC JESD89A requires using either broad beam neutron sources or at least four single neutron/proton particle energy sources. While computing ambient upset rates from broad beam neutron sources, such as the ICE House at Los Alamos Neutron Science Center (LANSCE), is simple and direct, their availability, cost, and particle fluxes are very limited. Several authors in the open literature therefore have considered alternatives, such as high energy (e.g., 200 MeV) proton beams or low energy (e.g., 14MeV) neutron beams. In this paper, we address the questions of accuracy and correlation when these alternative facilities are employed. SEU data were collected on 22nm Tri-Gate bulk CMOS devices at Boeing (BrEL), Los Alamos (LANSCE/WNr) and IUCF (rErP and LENS) and the corresponding upset rates are compared.

关键词： Neutrons Particle beams Latches Protons Lenses random access memory Single event upsets

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Gate dielectric TDDB characterizations of advanced High-k and metal-gate CMOS logic transistor technology

Gate dielectric TDDB characterizations of advanced High-k an...

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Annual International Symposium on reliability Physics

作者： S. Pae C. Prasad S. ramey J. Thomas A. rahman r. Lu J. Hicks S. Batzer q. Zhao J. Hatfield M. Liu C. Parker B. Woolery Intel Corporation LTD Q&R ICF Q&R Portland Technology Development Hillsboro OR

Transition into High-K (HK) dielectric and Metal-Gate (MG) in advanced logic process has enabled continued technology scaling in support of Moore's law [1-2]. With this, CMOS operating fields have been increasing along with gate dielectric TDDB voltage acceleration factors (VAF). VAF is the most critical reliability parameter used to accurately predict the Gate oxide lifetime (TDDB) at use. This paper highlights low voltage (low-V) TDDB data is critical for the accurate assessment of HK+MG VAF and provides further evidences from both transistor- and product-level data based on 32nm technology generations.

关键词： Stress logic gates MOS devices reliability Dielectrics Extrapolation High K dielectric materials

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reliability characterization of 32nm high-K and Metal-Gate logic transistor technology

Reliability characterization of 32nm high-K and Metal-Gate l...

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Annual International Symposium on reliability Physics

作者： Sangwoo Pae Ashwin Ashok Jingyoo Choi Tahir Ghani Jun He Seok-hee Lee Karen Lemay Mark Liu ryan Lu Paul Packan Chris Parker richard Purser Anthony St. Amour Bruce Woolery Q&R Intel Corporation Limited Hillsboro OR USA DID Manufacturing Hillsboro OR USA Hillsboro OR USA Portland Technology Development Hillsboro OR USA

ISBN: (纸本)9781424454303;9781424454310

High-K (HK) and Metal-Gate (MG) transistor reliability is very challenging both from the standpoint of introduction of new materials and requirement of higher field of operation for higher performance. In this paper, key and unique HK+MG intrinsic transistor reliability mechanisms observed on 32nm logic technology generation is presented. We'll present intrinsic reliability similar to or better than 45nm generation.

关键词： High K dielectric materials High-K gate dielectrics logic MOS devices Materials reliability Silicon germanium Germanium silicon alloys Electric breakdown Tunneling Capacitive sensors

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Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology

Characterization of SILC and its end-of-life reliability ass...

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Annual International Symposium on reliability Physics

作者： S. Pae T. Ghani M. Hattendorf J. Hicks J. Jopling J. Maiz K. Mistry J. O'Donnell C. Prasad J. Wiedemer J. Xu Logic Technology Development Q&R Intel Corporation Hillsboro OR USA Portland Technology Development Hillsboro OR Intel Corporation Logic Technology Development Q&R Hillsboro USA Intel Corporation Logic Technology Development Q&R

Stress induced leakage current (SILC) has been observed on non-optimized high-K (HK) and metal-gate (MG) transistors. Large NMOS PBTI degradation and correlation to SILC increase on such gate stack is a result of large trap generations in the bulk-HK. This poses a long term reliability concern on product standby power and can limit the operating voltage if not suppressed. On an optimized HK+MG process, we demonstrate that SILC has been suppressed. The transistor level SILC data, model and product burn-in stress data support this. With optimized process, SILC has no impact on products made of 45 nm HK+MG transistors.

关键词： High K dielectric materials High-K gate dielectrics Stress MOS devices Gate leakage Electron traps Leakage current Degradation Voltage Transistors

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BTI reliability of 45 nm high-K + metal-gate process technology

BTI reliability of 45 nm high-K + metal-gate process technol...

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Annual International Symposium on reliability Physics

作者： S. Pae M. Agostinelli M. Brazier r. Chau G. Dewey T. Ghani M. Hattendorf J. Hicks J. Kavalieros K. Kuhn M. Kuhn J. Maiz M. Metz K. Mistry C. Prasad S. ramey A. roskowski J. Sandford C. Thomas J. Thomas C. Wiegand J. Wiedemer Logic Technology Development Q&R USA PTD USA Intel Corporation Hillsboro OR USA

In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized HK film stack in the early development phase exhibited pre-existing traps and large amount of hysteresis that was consistent with literature. The optimized and final HK process demonstrated NMOS and PMOS BTI on HK+MG transistors that are better than that of SiON at matched E-fields and comparable at targeted 30% higher use fields. The final process also showed no hysteresis due to fast traps thereby allowing us to characterize its intrinsic degradation mechanism. On the optimized process, NMOS BTI is attributed primarily to electron trapping in the HK bulk and HK/SiON interfacial layer (IL) regions. PMOS BTI degradation, on the other hand, is mainly interface driven and is found to be very similar to that observed on conventional SiON transistors.

关键词： High K dielectric materials High-K gate dielectrics MOS devices Gate leakage Hysteresis Leakage current Electron traps Thermal degradation Electrodes logic

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Multi-cell upset probabilities of 45nm high-k + metal gate SrAM devices in terrestrial and space environments

Multi-cell upset probabilities of 45nm high-k + metal gate S...

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Annual International Symposium on reliability Physics

作者： N. Seifert B. Gill K. Foley P. relangi Logic Technology Development Q&R Intel Corporation Hillsboro OR USA Architecture for Quality and Reliability Intel Corporation Hillsboro OR USA Design and Technology Solutions Intel Corporation Hillsboro OR USA Department of Electrical Engineering University of Stanford Stanford CA USA

Multi-cell soft errors are a key reliability concern for advanced memory devices. We have investigated single-bit (SBU) and multi-cell upset (MCU) rates of SrAM devices built in a 45 nm high-k + metal gate (HK+MG) technology under neutron, proton and heavy-ion radiation. Our data highlight the excellent soft error reliability scaling properties of HK+MG. MCU rates were kept at 10% or less of SBU ones and bit-level SBU rates continue to decrease 2times per technology generation for terrestrial applications. SrAM upset rates in orbit are projected to be 2 to 4 orders of magnitude higher than at sea-level. A dramatic increase in MCU rates relative to SBU is projected for geosynchronous orbits, where direct ionization by heavy-ions dominates. No indication of charge amplification by parasitic bipolar devices has been observed for all investigated radiation environments. The observation that SBU error rates and small MCU error rates are elevated at locations in close proximity to well contacts for high LET values is speculated to be the result of the formation of a funnel between well contacts and sensitive drains.

关键词： High K dielectric materials High-K gate dielectrics random access memory Error analysis Protons Space technology Neutrons Ionization Error correction codes logic devices

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Multi-cell upset probabilities of 45nm high-k + metal gate SrAM devices in terrestrial and space environments

Multi-cell upset probabilities of 45nm high-k + metal gate S...

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46th Annual 2008 IEEE International reliability Physics Symposium, IrPS

作者： Seifert, N. Gill, B. Foley, K. relangi, P. Logic Technology Development Q and R Intel Corporation Hillsboro OR 97124 United States Architecture for Quality and Reliability Intel Corporation Hillsboro OR 97124 United States Design and Technology Solutions Intel Corporation Hillsboro OR 97124 United States Stanford University Dept. of Electrical Engineering Stanford CA 94305 United States

ISBN: (纸本)9781424420506

Multi-cell soft errors are a key reliability concern for advanced memory devices. We have investigated single-bit (SBU) and multi-cell upset (MCU) rates of SrAM devices built in a 45nm high-k + metal gate (HK+MG) technology under neutron, proton and heavy-ion radiation. Our data highlight the excellent soft error reliability scaling properties of HK+MG. MCU rates were kept at 10% or less of SBU ones and bit-level SBU rates continue to decrease 2 per technology generation for terrestrial applications. SrAM upset rates in orbit are projected to be 2 to 4 orders of magnitude higher than at sea-level. A dramatic increase in MCU rates relative to SBU is projected for geosynchronous orbits, where direct ionization by heavy-ions dominates. No indication of charge amplification by parasitic bipolar devices has been observed for all investigated radiation environments. The observation that SBU error rates and small MCU error rates are elevated at locations in close proximity to well contacts for high LET values is speculated to be the result of the formation of a funnel between well contacts and sensitive drains. © 2008 IEEE.

关键词： Static random access storage

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