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BTI reliability of 45 nm high-k + metal-gate process technology

BTI reliability of 45 nm high-k + metal-gate process technol...

引用

46th Annual 2008 IEEE International reliability Physics Symposium, IrPS

作者： Pae, S. Agostinelli, M. Brazier, M. Chau, r. Dewey, G. Ghani, T. Hattendorf, M. Hicks, J. Kavalieros, J. Kuhn, K. Kuhn, M. Maiz, J. Metz, M. Mistry, K. Prasad, C. ramey, S. roskowski, A. Sandford, J. Thomas, C. Thomas, J. Wiegand, C. Wiedemer, J. Logic Technology Development Q and R Intel Corporation 5200 N.E. Elam Young Pkwy. Hillsboro OR 97124 United States PTD Intel Corporation 5200 N.E. Elam Young Pkwy. Hillsboro OR 97124 United States CR Intel Corporation 5200 N.E. Elam Young Pkwy. Hillsboro OR 97124 United States

ISBN: (纸本)9781424420506

In this paper, Bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an un-optimized HK film stack in the early development phase exhibited pre-existing traps and large amount of hysteresis that was consistent with literature. The optimized and final HK process demonstrated NMOS and PMOS BTI on HK+MG transistors that are better than that of SiON at matched E-fields and comparable at targeted 30% higher use fields. The final process also showed no hysteresis due to fast traps thereby allowing us to characterize its intrinsic degradation mechanism. On the optimized process, NMOS BTI is attributed primarily to electron trapping in the HK bulk and HK/SiON interfacial layer (IL) regions. PMOS BTI degradation, on the other hand, is mainly interface driven and is found to be very similar to that observed on conventional SiON transistors. © 2008 IEEE.

关键词： Silicon compounds

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Effect of NBTI degradation on transistor variability in advanced technologies

Effect of NBTI degradation on transistor variability in adva...

引用

IEEE International Workshop Integrated reliability

作者： S. Pae J. Maiz C. Prasad Logic Technology Development Q&R Intel Corporation Hillsboro OR USA

The effect of PMOS Negative Bias Temperature Instability (NBTI) on product performance is a concern. As technology scales and device dimension shrinks, the trend in the Vt-variability at both time zero and after NBTI aging increases. The timeO Vt- variability can be explained by the random nature of dopants, whereas the randomly generated defects in the gate oxide can account for the device aging-induced variability. This paper focuses on the NBTI-induced device Vt-variability and trend across technology generations. The remarkable correlation of aging-induced Vt-variability to the gate oxide area suggests that the geometry scaling is the dominant component that drives the increased trend in aging-induced variability.

关键词： Niobium compounds Titanium compounds Degradation Transistors Aging logic devices random access memory Negative bias temperature instability Geometry Dielectrics

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Sensitivity Investigation of Substrate Thickness and reflow Profile on Wafer Level Film Failures in 3D Chip Scale Packages by Finite Element Modeling

Sensitivity Investigation of Substrate Thickness and Reflow ...

引用

Electronic Components and technology Conference (ECTC)

作者： Bin Xie Xunqing Shi Xuejun Fan Advanced Electronic Manufacturing Center Shanghai Jiaotong University Shanghai China Flash Manufacturing Group Intel Technology Development (Shanghai) Company Limited Shanghai China Q&R Assembly Technology Development Intel Corporation Chandler AZ USA

3D chip scale package (CSP) is one of the major trends in IC packaging with the application of wafer level films (WLF) for die-to-die or die-to-substrate attachment. However, the WLF failures (voiding/cracking) are often observed in moisture sensitivity test. Substrate thickness and reflow profile were found very sensitive to the WLF failure rate. To investigate the sensitivity of the substrate thickness and the reflow profile, a novel direct concentration approach (DCA) is developed in this study, which allows updating the interfacial continuous condition as the function of the temperature and humidity. The paper also develops a simplified micromechanics-based vapor pressure model to visualize the whole-field vapor pressure corresponding to the instantaneous moisture distribution. With the applications of the DCA and the simplified vapor pressure model to a 3D ultra-thin stacked-die CSP, it was found that the moisture transport and escape during the reflow is the root cause of the WLF failures. A small reduction of the substrate thickness and an in-situ baking during the reflow can reduce greatly the moisture concentration and the vapor pressure at the bottom film, and therefore significantly decrease the WLF failure rate.

关键词： Substrates Chip scale packaging Wafer scale integration Finite element methods Semiconductor device modeling Moisture Integrated circuit packaging Integrated circuit modeling Testing Temperature sensors

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On the Scalability of redundancy based SEr Mitigation Schemes

On the Scalability of Redundancy based SER Mitigation Scheme...

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IEEE International Conference on Integrated Circuit Design and technology (ICICDT)

作者： N. Seifert B. Gill V. Zia M. Zhang V. Ambrose Logic Technology Development Q & R Intel Corporation Hillsboro OR USA Architecture for Quality and Reliability Intel Corporation Hillsboro OR USA Enterprise Microprocessor Group Intel Corporation Hillsboro OR USA Mobility Group Intel Corporation Folsom CA USA Enterprise Microprocessor Group Intgel Corporation Hudson MA USA

A novel circuit-level simulation strategy to assess the impact of charge sharing on the upset rate of redundancy based radiation hardened designs is introduced. Accelerated measurements conducted at the Los Alamos National Laboratory show a 10s or better reliability of hardened latches over standard latches for 45nm and 90nm implementations. Despite this encouraging trend, our simulations project that compact redundancy hardened designs will have soft error rates similar to non-hardened designs within a few technology generations if no additional mitigation techniques are applied to reduce the impact of charge sharing.

关键词： Scalability redundancy Circuit simulation Error analysis radiation hardening Space technology Computational modeling Clocks Latches random access memory

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radiation-Induced Soft Error rates of Advanced CMOS Bulk Devices

Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Dev...

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Annual International Symposium on reliability Physics

作者： N. Seifert P. Slankard M. Kirsch B. Narasimham V. Zia C. Brookreson A. Vo S. Mitra B. Gill J. Maiz Logic Technology Development Q&R Intel Corporation Hillsboro OR USA Department of Electrical Engineering and Computer Science Vanderbilt University Nashville TN USA Enterprise Microprocessor Group Intel Corporation Hillsboro OR USA Digital Enterprise Group Q&R Intel Corporation Hillsboro OR USA Logic Technology Development Q&R Intel Corporation Folsom CA USA Department of Electrical Engineering University of Stanford Stanford CA USA

This work provides a comprehensive summary of radiation-induced soft error rate (SEr) scaling trends of key CMOS bulk devices. Specifically we analyzed the SEr per bit scaling trends of SrAMs, sequentials and static combinational logic. Our results show that for SrAMs the single-bit soft error rate continues to decrease whereas the multi-bit SEr increases dramatically. While the total soft error rate of logic devices (sequentials and static combinational devices) has not changed significantly, a substantial increase in the susceptibility to alpha particles is observed. Finally, a novel methodology to extract one-dimensional cross sections of the collected charge distributions from measured multi-bit statistics is introduced

关键词： Error analysis logic devices random access memory Neutrons Testing Interleaved codes CMOS logic circuits CMOS technology Microprocessors Alpha particles

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Effects of Hot Carrier Stress on reliability of Strained-Si Mosfets

Effects of Hot Carrier Stress on Reliability of Strained-Si ...

引用

Annual International Symposium on reliability Physics

作者： S. Dey M. Agostinelli C. Prasad X. Wang L. Shifren Microelectronics Research Center University of Texas Austin Austin TX USA Technology Development Q&R Intel Corporation Hillsboro OR USA

The focus of this work is to demonstrate the effect of mechanical stress in the channel on the impact ionization rate (IIr) and on hot carrier reliability for both NMOS and PMOS devices. In addition, this study will explain the reason for the wide disagreement between published reports on this behavior. It is shown for the first time that the IIr reaches a maximum value with strain for NMOS and then reduces as higher levels of strain are applied. Compressive strained PMOS devices do not show this peak in IIr

关键词： Hot carriers MOSFETs Capacitive sensors MOS devices Impact ionization Tensile stress Photonic band gap Strain measurement Scattering Compressive stress

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Erratic fluctuations of sram cache vmin at the 90nm process technology node

Erratic fluctuations of sram cache vmin at the 90nm process ...

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International Electron Devices Meeting (IEDM)

作者： M. Agostinelli J. Hicks J. Xu B. Woolery K. Mistry K. Zhang S. Jacobs J. Jopling W. Yang B. Lee T. raz M. Mehalel P. Kolar Y. Wang J. Sandford D. Pivin C. Peterson M. DiBattista S. Pae M. Jones S. Johnson G. Subramanian Logic TD Q&R Intel Corporation Hillsboro OR USA Portland Technology Development Intel Corporation Hillsboro OR USA Portland Technology Development FSM Q&R IDC Q&R

Erratic bit phenomena have been reported in advanced flash memories, and have been attributed to trapping/detrapping effects that modify the threshold voltage. This paper describes for the first time the observance of erratic behavior in SrAM Vmin, defined as the minimum voltage at which the SrAM array is functional. random telegraph signal (rTS) noise in the soft breakdown gate leakage is shown to be the cause. The erratic Vmin phenomenon can be eliminated for 90 nm SrAMs by process optimization. However, erratic Vmin behavior gets worse with smaller cell sizes and represents another constraint on the scaling of SrAM cells and on the minimum operating voltage of the SrAM array. A combination of process and circuit solutions will likely be needed to enable continued SrAM cell scaling

关键词： Fluctuations random access memory Sampling methods Electric breakdown Probability distribution Flash memory Threshold voltage Electron traps logic arrays Jacobian matrices

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Node sensitivity analysis for soft errors in CMOS logic

Node sensitivity analysis for soft errors in CMOS logic

引用

IEEE International Test Conference, ITC 2005

作者： Gill, Balkaran S. Papachristou, Chris Wolff, Francis G. Seifert, Norbert Department of Electrical Engineering and Computer Science Case Western Reserve University Cleveland OH Logic Technology Development Q and R Intel Corporation Hillsboro OR

ISBN: (纸本)0780390393

In this paper, we introduce an approach for computing soft error susceptibility of nodes in large CMOS circuits at the transistor level. The node sensitivity depends on the electrical, logic, and timing masking. An efficient technique is developed to compute the electrical masking of nodes using characterization tables and inverse pulse propagation. We generated these tables for every logic cell of the library using Spice simulations for a 100nm process technology. An additional technique to compute the logic masking of the transistor nodes using an automatic test pattern generation tool is described. Our results show that our approach has Spice like accuracy but it is several orders of magnitude faster than Spice. This approach can be used to analyze the vulnerability of circuits to single event upsets at the chip level. results are provided for ISCAS85 benchmark circuits. © 2005 IEEE.

关键词： CMOS integrated circuits

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Node sensitivity analysis for soft errors in CMOS logic

Node sensitivity analysis for soft errors in CMOS logic

引用

IEEE International Test Conference

作者： B.S. Gill C. Papachristou F.G. Wolff N. Seifert Department of Electrical Engineering and Computer Science Case Western Reserve University Cleveland OH USA Logic Technology Development Q&R Intel Corporation Hillsboro OR USA

In this paper, we introduce an approach for computing soft error susceptibility of nodes in large CMOS circuits at the transistor level. The node sensitivity depends on the electrical, logic, and timing masking. An efficient technique is developed to compute the electrical masking of nodes using characterization tables and inverse pulse propagation. We generated these tables for every logic cell of the library using Spice simulations for a 100 nm process technology. An additional technique to compute the logic masking of the transistor nodes using an automatic test pattern generation tool is described. Our results show that our approach has Spice like accuracy but it is several orders of magnitude faster than Spice. This approach can be used to analyze the vulnerability of circuits to single event upsets at the chip level. results are provided for ISCAS85 benchmark circuits

关键词： Sensitivity analysis CMOS logic circuits Timing Libraries Computational modeling Circuit simulation Automatic logic units logic testing Automatic test pattern generation Single event upset

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random charge effects for PMOS NBTI in ultra-small gate area devices

Random charge effects for PMOS NBTI in ultra-small gate area...

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Annual International Symposium on reliability Physics

作者： M. Agostinelli S. Pae W. Yang C. Prasad D. Kencke S. ramey E. Snyder S. Kashyap M. Jones Technology Development Q&R Intel Corporation Hillsboro OR USA Technology CAD Intel Corporation Hillsboro OR USA AMI Semiconductors Inc. Pocatello ID USA Data Products Group Q&R Intel Corporation Folsom CA USA

PMOS transistor degradation due to negative bias temperature instability (NBTI) has been shown to be a major transistor reliability mechanism. The effect of PMOS NBTI on the minimum operating voltage of a cache cell (Vmin) has been recently demonstrated, and the modeling of the degradation of ultra small gate area devices is vital for the accurate modeling of Vmin. recent data and simulation has indicated that random fluctuations in device degradation are present under stress. This paper examines the source of these random fluctuations in device degradation due to PMOS NBTI.

关键词： Niobium compounds Titanium compounds Degradation Fluctuations Threshold voltage Stress Current density Semiconductor process modeling Impurities Poisson equations

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