Low frequency noise (1/f noise) poses a major limitation to analog and radio frequency (rF) integrated circuits (IC) as device dimensions are scaled down. The reduction in device dimensions leads to substantial hot ca...
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Low frequency noise (1/f noise) poses a major limitation to analog and radio frequency (rF) integrated circuits (IC) as device dimensions are scaled down. The reduction in device dimensions leads to substantial hot carrier effects and causes increased 1/f noise degradation. This noise degradation has been demonstrated to be detrimental to the functioning of analog mixed signal and rF ICs. Previous work has shown that 1/f noise degradation can be correlated to drain current degradation, but no differentiation of the noise degradation has been made as a function of bias regime or oxide thickness. In this paper, the noise degradation effects in both thin and thick gate oxide NMOS transistors are characterized across different regimes of stress and measurement bias. It is demonstrated that the effect of hot electron stress on 1/f noise in ultra-thin gate oxide transistors is very different from thick gate devices. In addition, it is shown for the first time that the electrical stress regime has a large effect on 1/f noise degradation.
The paper assesses the reliability risk due to radiation-induced single event upsets (SEU) of clock nodes for flip flop and pulse latch based designs. Two basic upset modes are identified: radiation-induced clock jitt...
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The paper assesses the reliability risk due to radiation-induced single event upsets (SEU) of clock nodes for flip flop and pulse latch based designs. Two basic upset modes are identified: radiation-induced clock jitter and radiation-induced race. Our simulation results indicate that the radiation-induced clock soft errorrate (SEr) cannot be neglected on the chip-level. Particularly for pulse latch based designs, upsets occurring in the clock generator have the potential to dominate the chip-level SEr if no mitigation techniques are applied. Ourresults show that the hardened pulse latch in combination with a hardened and shared pulse generator yields a 20/spl times/ improvement in sequential SEr as well as the lowest susceptibility to radiation-induced race and clock jitter with little area and performance penalty.
This study assesses the reliability risk due to radiation-induced single event upsets (SEU) of clock nodes for flip flop and pulse latch based designs. Two basic upset modes are identified: radiation-induced clock jit...
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The effect of oxide soft breakdown (SBD) on the reliability of a 6-T cache cell has been examined and a circuit based gate oxide (GOX) reliability model has been developed. The results show that a model that combines ...
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The effect of oxide soft breakdown (SBD) on the reliability of a 6-T cache cell has been examined and a circuit based gate oxide (GOX) reliability model has been developed. The results show that a model that combines the circuit topology, PMOS bias temperature (PMOS BT) effect, and a SBD time dependent leakage model allows for accurate prediction of the observed vccmin test voltage dependence. Through simulation it was determined that PMOS BT plays a significant role in aggravating SBD effects on stability. Examples are shown of cell stability using a simplified circuit SBD model including varying amounts of PMOS BT degradation on the two PMOS pull up devices, a SBD time evolution model for NMOS devices is explained, and finally a comprehensive model combining all of these effects is presented along with initial data verifying model trends.
PMOS transistor degradation due to Negative Bias Temperature Instability (NBTI) has proven to be a significant concern to present CMOS technologies. This is of particular concern for analog applications where the abil...
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PMOS transistor degradation due to Negative Bias Temperature Instability (NBTI) has proven to be a significant concern to present CMOS technologies. This is of particular concern for analog applications where the ability to match device characteristics to a high precision is critical. Analog circuits use larger than minimum device dimensions to minimize the effects of process variation, leaving PMOS NBTI as a possible performance limiter. This paper examines the effect of PMOS NBTI induced mismatch on analog circuits in a 90nm technology.
In this paper, the reliability of the vertical drain NMOS (VDNMOS) device structure has been evaluated for a state of the art CMOS process. In past technologies, reliability was restricted by hot carrier degradation e...
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In this paper, the reliability of the vertical drain NMOS (VDNMOS) device structure has been evaluated for a state of the art CMOS process. In past technologies, reliability was restricted by hot carrier degradation effects. With technology scaling, gate oxide wear-out has become the reliability limiter. A new VDNMOS oxide wear-out model has been developed and verified with low voltage stress data. This new model accurately captures the dependence of VDNMOS lifetime on drain to gate bias and can be used to better project the maximum drain voltage at operating condition.
PMOS transistor degradation due to Negative Bias Temperature Instability (NBTI) has proven to be significant concern to present CMOS technologies. This is of particular concern for analog applications where the abilit...
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PMOS transistor degradation due to Negative Bias Temperature Instability (NBTI) has proven to be significant concern to present CMOS technologies. This is of particular concern for analog applications where the ability to match device characteristics to a high precision is critical. Analog circuits use larger than minimum device dimensions to minimize the effects of process variation, leaving PMOS NBTI as a possible performance limiter. This paper examines the effect of PMOS NBTI induced mismatch on analog circuits in a 90 nm technology.
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