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检索条件"机构=Logic Technology Development Quality and Reliability"
48 条 记 录,以下是1-10 订阅
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A detailed comparison of various off-state breakdown methodologies for scaled Tri-gate technologies
A detailed comparison of various off-state breakdown methodo...
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Annual International Symposium on reliability Physics
作者: K. Joshi D. Nminibapiel M. Ghoneim D. Ali R. Ramamurthy L. Pantisano I. Meric S. Ramey Logic Technology Development Quality and Reliability Intel Corporation Hillsboro OR USA
The source-drain punch-through current in off-state TDDB stress (OSS) is shown to significantly affect off-state breakdown behavior. This paper compares various OSS methodologies available in the literature and discus... 详细信息
来源: 评论
Assessing Impact of Non-Uniform Localized Heating on reliability
Assessing Impact of Non-Uniform Localized Heating on Reliabi...
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IEEE International Conference on Interconnect technology
作者: Yoon Jo Kim Edwin B. Ramayya Lei Jiang Jason Jopling Rahim Kasim Logic Technology Development Quality and Reliability Intel Corporation Hillsboro Oregon U.S.A Logic Technology Development Intel Corporation Hillsboro Oregon U.S.A
Moore’s Law-driven technology improvements have led to a significant increase in power density across a multitude of market segments, from mobile to HEDT (high-end desktop) and servers. This, in turn, has led to an i... 详细信息
来源: 评论
A Unified Aging Model Framework Capturing Device to Circuit Degradation for Advance technology Nodes
A Unified Aging Model Framework Capturing Device to Circuit ...
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Annual International Symposium on reliability Physics
作者: S. Mukhopadhyay C. Chen M. Jamil J. Standfest I. Meric B. Gill S. Ramey Logic Technology Development Quality and Reliability Intel Corporation USA Quality & Reliability Test Chip Design and Data Intel Corporation USA
Transistor aging under complex input waveform stress has been a key concern for device and circuit reliability. The overall Design technology Co-Optimization (DTCO) is strongly guided by the reliability risk of a sing... 详细信息
来源: 评论
reliability Studies on Advanced FinFET Transistors of the Intel 4 CMOS technology
Reliability Studies on Advanced FinFET Transistors of the In...
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Annual International Symposium on reliability Physics
作者: M. Jamil S. Mukhopadhay M. Ghoneim A. Shailos C. Prasad I. Meric S. Ramey Logic Technology Development Quality and Reliability Intel Corporation Hillsboro Oregon U.S.A.
The Intel 4 CMOS FinFET technology delivers over 20% performance gains at iso-power over the prior generation (Intel 7). This paper reports reliability studies on the Intel 4 technology that demonstrate matched or bet... 详细信息
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reliability Modeling of Middle-Of-Line Interconnect Dielectrics in Advanced process nodes
Reliability Modeling of Middle-Of-Line Interconnect Dielectr...
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Annual International Symposium on reliability Physics
作者: R. Kasim C. Lin C. Perini J. Palmer N. Gilda S. Imam J. R. Weber C. Wallace J. Hicks Logic Technology Development Quality and Reliability Intel Corporation Hillsboro OR USA TCAD Intel Corporation Hillsboro OR USA Portland Technology Development Intel Corporation Hillsboro OR USA
This paper discusses the physics and methodology for estimating the reliability lifetime of MOL (Middle-Of-Line) dielectrics for advanced process nodes. Both intrinsic and defect reliability aspects of MOL dielectrics... 详细信息
来源: 评论
A Physical Unclonable Function Leveraging Hot Carrier Injection Aging
A Physical Unclonable Function Leveraging Hot Carrier Inject...
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Annual International Symposium on reliability Physics
作者: Rachael J. Parker Jyothi Bhaskarr A. Velamala Kuan-Yueh James Shen David Johnston Yao-Feng Chang Stephen M. Ramey Siang-Jhih Sean Wu Padma Penmatsa Design Engineering Group Intel Corporation Hillsboro OR U.S.A Logic Technology Development Quality & Reliability Intel Corporation Hillsboro OR U.S.A Manufacturing and Product Engineering Intel Corporation Folsom CA U.S.A
Physical Unclonable Functions (PUFs) are low-cost cryptographic primitives used to generate unique, secure, and stable IDs for device authentication and secure communication. PUFs rely on process variation inherent in... 详细信息
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Novel Re-configurable Circuits For Aging Characterization: Connecting Devices to Circuits
Novel Re-configurable Circuits For Aging Characterization: C...
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Annual International Symposium on reliability Physics
作者: Ketul B. Sutaria Jihan Standfest Inanc Meric Amirhossein H. Davoody Swaroop Kumar Namalapuri T. Mutyala Supriya P. Balkaran Gill Stephen Ramey Jeffery Hicks Logic Technology Development Quality and Reliability Hillsboro Oregon
Circuit reliability is a significant concern in scaled technologies. Physical aging models derived by DC stress on discrete devices are accurate to an extent, but can be further improved by evaluating the behaviour of...
来源: 评论
Modeling Framework for Transistor Aging Playback in Advanced technology Nodes
Modeling Framework for Transistor Aging Playback in Advanced...
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Annual International Symposium on reliability Physics
作者: I. Meric S. Ramey S. Novak S. Gupta S. P. Mudanai J. Hicks Logic Technology Development Quality and Reliability Pre-Silicon Quality and Reliability Logic Technology Development Advanced Design Intel Co Hillsboro Oregon U.S.A
With continuous channel length scaling and ongoing demand for higher operating frequencies, HCI degradation and combining BTI and HCI aging mechanisms in compact aging models becomes important for accurately capturing...
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On the Correlation of Laser-induced and High-Energy Proton Beam-induced Single Event Latchup
On the Correlation of Laser-induced and High-Energy Proton B...
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Annual International Symposium on reliability Physics
作者: Bahar Ajdari Samwel Sekwao Ricardo Ascazubi Adam Neale Norbert Seifert Product Reliability Services Corporate Quality Network Intel Corporation Hillsboro OR Logic Technology Development Q&R Corporate Quality Network Intel Corporation Hillsboro OR 97124
We report on pulsed laser and high-energy proton induced Single Event Latchup (SEL) testing. Arrayed Silicon Controlled Rectifier (SCR) structures that implement various different layout design styles relevant to SEL ...
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Silicon reliability Characterization of Intel’s Foveros 3D Integration technology for logic-on-logic Die Stacking
Silicon Reliability Characterization of Intel’s Foveros 3D ...
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Annual International Symposium on reliability Physics
作者: Chetan Prasad Sunny Chugh Hannes Greve I-chen Ho Enamul Kabir Cheyun Lin Mahjabin Maksud Steven R. Novak Benjamin Orr Keun Woo Park Anthony Schmitz Zhizheng Zhang Peng Bai Doug B. Ingerly Emre Armagan Hsinwei Wu Patrick Stover Lance Hibbeler Michael O’Day Daniel Pantuso Logic Technology Development Quality and Reliability Intel Corporation Hillsboro OR U.S.A. Logic Technology Development Intel Corporation Hillsboro OR U.S.A. Assembly Test Technology Development Quality and Reliability Intel Corporation Chandler AZ U.S.A. Assembly Test Technology Development Intel Corporation Chandler AZ U.S.A. Technology Computed Aided Design Intel Corporation Hillsboro OR U.S.A.
This work presents silicon reliability characterization of Intel's Foveros three-dimensional (3D) logic-on-logic stacking technology implemented on the 22FFL process node. Simulations and data demonstrate mechanic...
来源: 评论