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检索条件"机构=Logic Technology Development Quality and Reliability"
48 条 记 录,以下是1-10 订阅
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Impact of interfacial chemistry on adhesion and electromigration in Cu interconnects
Impact of interfacial chemistry on adhesion and electromigra...
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Advanced Metallization Conference 2004, AMC 2004
作者: Zhou, Ying Scherban, Tracey Xu, Guanghai He, Jun Miner, Barbara Jan, Chia-Hong Ott, Andrew O'Loughlin, Jennifer Ingerly, Doug Leu, Jihperng Technology Development Quality and Reliability Logic Technology Development Intel Corporation Hillsboro OR 97124 Portland Technology Development Logic Technology Development Intel Corporation Hillsboro OR 97124
The impact of etch-stop (ES)/Cu interfacial chemistry on adhesion and electromigration (EM) has been systematically investigated by varying Cu surface chemistry, etch-stop film chemistry, metal capping layers, and the... 详细信息
来源: 评论
A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects  63
A 10nm high performance and low-power CMOS technology featur...
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63rd IEEE International Electron Devices Meeting, IEDM 2017
作者: Auth, C. Aliyarukunju, A. Asoro, M. Bergstrom, D. Bhagwat, V. Birdsall, J. Bisnik, N. Buehler, M. Chikarmane, V. Ding, G. Fu, Q. Gomez, H. Han, W. Hanken, D. Haran, M. Hattendorf, M. Heussner, R. Hiramatsu, H. Ho, B. Jaloviar, S. Jin, I. Joshi, S. Kirby, S. Kosaraju, S. Kothari, H. Leatherman, G. Lee, K. Leib, J. Madhavan, A. Maria, K. Meyer, H. Mule, T. Parker, C. Parthasarathy, S. Pelto, C. Pipes, L. Post, I. Prince, M. Rahman, A. Rajamani, S. Saha, A. Dacuna Santos, J. Sharma, M. Sharma, V. Shin, J. Sinha, P. Smith, P. Sprinkle, M. Amour, A.St. Staus, C. Suri, R. Towner, D. Tripathi, A. Tura, A. Ward, C. Yeoh, A. Logic Technology Development United States Quality and Reliability Engineering Intel Corporation United States
A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local interconnect layers is described. ... 详细信息
来源: 评论
A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171m2 SRAM cell size in a 291Mb array
A 32nm logic technology featuring 2nd-generation high-k + me...
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2008 IEEE International Electron Devices Meeting, IEDM 2008
作者: Natarajan, S. Armstrong, M. Bost, M. Brain, R. Brazier, M. Chang, C.-H. Chikarmane, V. Childs, M. Deshpande, H. Dev, K. Ding, G. Ghani, T. Golonzka, O. Han, W. He, J. Heussner, R. James, R. Jin, I. Kenyon, C. Klopcic, S. Lee, S.-H. Liu, M. Lodha, S. McFadden, B. Murthy, A. Neiberg, L. Neirynck, J. Packan, P. Pae, S. Parker, C. Pelto, C. Pipes, L. Sebastian, J. Seiple, J. Sell, B. Sivakumar, S. Song, B. Tone, K. Troeger, T. Weber, C. Yang, M. Yeoh, A. Zhang, K. Logic Technology Development United States Quality and Reliability Engineering United States TCAD Intel Corporation United States
A 32nm generation logic technology is described incorporating 2 nd-generation high-k + metal-gate technology, 193nm immersion lithography for critical patterning layers, and enhanced channel strain techniques. The tra... 详细信息
来源: 评论
reliability for manufacturing on 45nm logic technology with high-k + metal gate transistors and Pb-free packaging
Reliability for manufacturing on 45nm logic technology with ...
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2009 IEEE International reliability Physics Symposium, IRPS 2009
作者: Kasim, Rahim Connor, Chris Hicks, Jeff Jopling, Jason Litteken, Chris Logic Technology Development Quality and Reliability Intel Corporation 5200 N.E. ElamYoung Pkwy Hillsboro OR 97124 United States
This paper addresses several key aspects of integrated reliability for the Intel 45nm logic technology with high-K metal gate (HK+MG) transistors and Pb-free packaging. Significant changes in process architecture and ... 详细信息
来源: 评论
Novel Re-configurable Circuits For Aging Characterization: Connecting Devices to Circuits
Novel Re-configurable Circuits For Aging Characterization: C...
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Annual International Symposium on reliability Physics
作者: Ketul B. Sutaria Jihan Standfest Inanc Meric Amirhossein H. Davoody Swaroop Kumar Namalapuri T. Mutyala Supriya P. Balkaran Gill Stephen Ramey Jeffery Hicks Logic Technology Development Quality and Reliability Hillsboro Oregon
Circuit reliability is a significant concern in scaled technologies. Physical aging models derived by DC stress on discrete devices are accurate to an extent, but can be further improved by evaluating the behaviour of...
来源: 评论
Modeling Framework for Transistor Aging Playback in Advanced technology Nodes
Modeling Framework for Transistor Aging Playback in Advanced...
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Annual International Symposium on reliability Physics
作者: I. Meric S. Ramey S. Novak S. Gupta S. P. Mudanai J. Hicks Logic Technology Development Quality and Reliability Pre-Silicon Quality and Reliability Logic Technology Development Advanced Design Intel Co Hillsboro Oregon U.S.A
With continuous channel length scaling and ongoing demand for higher operating frequencies, HCI degradation and combining BTI and HCI aging mechanisms in compact aging models becomes important for accurately capturing...
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Practical implications of chip-level statistical electromigration
Practical implications of chip-level statistical electromigr...
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Annual International Symposium on reliability Physics
作者: Anthony Schmitz Logic Technology Development Quality and Reliability Intel Corporation Hillsboro OR USA
The accurate setting of electromigration (EM) design guidelines early is necessary to achieve chip-level fail goals. The issue is even more critical with the recognition of the percentage fail as a stochastic issue ba... 详细信息
来源: 评论
reliability for manufacturing on 45nm logic technology with high-k + metal gate transistors and Pb-free packaging
Reliability for manufacturing on 45nm logic technology with ...
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Annual International Symposium on reliability Physics
作者: Rahim Kasim Chris Connor Jeff Hicks Jason Jopling Chris Litteken Logic Technology Development Quality and Reliability Intel Corporation Hillsboro OR USA
This paper addresses several key aspects of integrated reliability for the Intel 45 nm logic technology with high-K metal gate (HK + MG) transistors and Pb-free packaging. Significant changes in process architecture a... 详细信息
来源: 评论
Susceptibility of planar and 3D tri-gate technologies to muon-induced single event upsets
Susceptibility of planar and 3D tri-gate technologies to muo...
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Annual International Symposium on reliability Physics
作者: Norbert Seifert Shah Jahinuzzaman Jyothi Velamala Nikunj Patel Logic Technology Development Quality and Reliability Intel Corporation Hillsboro OR USA
We report on muon-induced single event upsets (SEU) in SRAMs built on 32nm planar and 22nm and 14nm 3D Tri-Gate technologies. Experimental cross sections were measured using the M20C positive muon beamline at TRIUMF. ... 详细信息
来源: 评论
A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array
A 32nm logic technology featuring 2nd-generation high-k + me...
收藏 引用
International Electron Devices Meeting (IEDM)
作者: S. Natarajan M. Armstrong M. Bost R. Brain M. Brazier C.-H. Chang V. Chikarmane M. Childs H. Deshpande K. Dev G. Ding T. Ghani O. Golonzka W. Han J. He R. Heussner R. James I. Jin C. Kenyon S. Klopcic S.-H. Lee M. Liu S. Lodha B. McFadden A. Murthy L. Neiberg J. Neirynck P. Packan S. Pae C. Parker C. Pelto L. Pipes J. Sebastian J. Seiple B. Sell S. Sivakumar B. Song K. Tone T. Troeger C. Weber M. Yang A. Yeoh K. Zhang Logic Technology Development Quality and Reliability Engineering TCAD Intel Corporation
A 32 nm generation logic technology is described incorporating 2 nd -generation high-k + metal-gate technology, 193 nm immersion lithography for critical patterning layers, and enhanced channel strain techniques. The ... 详细信息
来源: 评论