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A detailed comparison of various off-state breakdown methodologies for scaled Tri-gate technologies

A detailed comparison of various off-state breakdown methodo...

引用

Annual International Symposium on reliability Physics

作者： K. Joshi D. Nminibapiel M. Ghoneim D. Ali R. Ramamurthy L. Pantisano I. Meric S. Ramey Logic Technology Development Quality and Reliability Intel Corporation Hillsboro OR USA

The source-drain punch-through current in off-state TDDB stress (OSS) is shown to significantly affect off-state breakdown behavior. This paper compares various OSS methodologies available in the literature and discusses how source-to-drain punch-through affects off-state breakdown and reliability. The proposed Drain-stress with Offset (DSO) OSS methodology limits punch-through to better reflect the actual field dependence of OSS breakdown for scaled tri-gate MOSFET technologies.

关键词： MOSFET Electric breakdown Estimation High-voltage techniques Aging logic gates reliability engineering

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Assessing Impact of Non-Uniform Localized Heating on reliability

Assessing Impact of Non-Uniform Localized Heating on Reliabi...

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IEEE International Conference on Interconnect technology

作者： Yoon Jo Kim Edwin B. Ramayya Lei Jiang Jason Jopling Rahim Kasim Logic Technology Development Quality and Reliability Intel Corporation Hillsboro Oregon U.S.A Logic Technology Development Intel Corporation Hillsboro Oregon U.S.A

ISBN: (数字)9798350385175

ISBN: (纸本)9798350385182

Moore’s Law-driven technology improvements have led to a significant increase in power density across a multitude of market segments, from mobile to HEDT (high-end desktop) and servers. This, in turn, has led to an increase in both spatial and temporal thermal non-uniformity across the chip. In this paper, thermally-induced reliability risks due to localized self-heat (thermomigration and thermal fatigue) were experimentally investigated. Novel test structures as well as experiments were devised to assess these risks. Thermomigration risk was demonstrated to be low at local temperature gradient up to 370 °C/μm. Accelerated EM failure manifested after a temperature gradient of approximately 500 °C/μm. The assessment of local thermal fatigue risk for contact-M4 layers indicated that they exhibited no failures through up to 10 billion thermal cycles, within peak temperature rise ranges of 220°C to 280°C.

关键词： Heating systems Temperature distribution Power system measurements Density measurement Fatigue reliability Servers

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A Unified Aging Model Framework Capturing Device to Circuit Degradation for Advance technology Nodes

A Unified Aging Model Framework Capturing Device to Circuit ...

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Annual International Symposium on reliability Physics

作者： S. Mukhopadhyay C. Chen M. Jamil J. Standfest I. Meric B. Gill S. Ramey Logic Technology Development Quality and Reliability Intel Corporation USA Quality & Reliability Test Chip Design and Data Intel Corporation USA

Transistor aging under complex input waveform stress has been a key concern for device and circuit reliability. The overall Design technology Co-Optimization (DTCO) is strongly guided by the reliability risk of a single transistor as well as by the reliability performance of the overall IP/product. Although the IP/Product reliability evaluation is most beneficial at the early stages of the technology development, it is often very expensive, and no certain aging model methodology exists to quantify the risks. In this work, for the first time we demonstrate a unified aging model framework, which not only can predict the traditional DC transistor aging, but also can accurately predict aging in various styles of circuits. Various Ring-Oscillators (RO) under arbitrary stress conditions are used to demonstrate model predictability after long-term stress approaching product use conditions. Such consistent framework helps to guide the process technology development, as well as provides for high-confidence product/IP reliability design assurance.

关键词： Aging Predictive models reliability engineering Silicon Product development Transistors Integrated circuit modeling

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reliability Studies on Advanced FinFET Transistors of the Intel 4 CMOS technology

Reliability Studies on Advanced FinFET Transistors of the In...

引用

Annual International Symposium on reliability Physics

作者： M. Jamil S. Mukhopadhay M. Ghoneim A. Shailos C. Prasad I. Meric S. Ramey Logic Technology Development Quality and Reliability Intel Corporation Hillsboro Oregon U.S.A.

The Intel 4 CMOS FinFET technology delivers over 20% performance gains at iso-power over the prior generation (Intel 7). This paper reports reliability studies on the Intel 4 technology that demonstrate matched or better reliability while extending Moore's law in the areas of power, performance, and scaling over its predecessor. Industry-leading technology scaling comes with numerous challenges, including co-optimization of yield, performance, and reliability. This paper reports the development of Intel 4 technology with industry-standard reliability while delivering significant advancement in generational performance and density.

关键词： Semiconductor device modeling Measurement Moore's Law Materials reliability Performance gain CMOS technology FinFETs

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reliability Modeling of Middle-Of-Line Interconnect Dielectrics in Advanced process nodes

Reliability Modeling of Middle-Of-Line Interconnect Dielectr...

引用

Annual International Symposium on reliability Physics

作者： R. Kasim C. Lin C. Perini J. Palmer N. Gilda S. Imam J. R. Weber C. Wallace J. Hicks Logic Technology Development Quality and Reliability Intel Corporation Hillsboro OR USA TCAD Intel Corporation Hillsboro OR USA Portland Technology Development Intel Corporation Hillsboro OR USA

This paper discusses the physics and methodology for estimating the reliability lifetime of MOL (Middle-Of-Line) dielectrics for advanced process nodes. Both intrinsic and defect reliability aspects of MOL dielectrics are investigated for accurate projection of reliability lifetime on Intel 4 process technology. Methods to deconvolute the impact of process driven variations on intrinsic Time Dependent Dielectric Breakdown (TDDB) are presented. In addition, a new construct for targeting of the MOL process parameters is also proposed to address challenges with technology scaling and to mitigate risk with pattern fidelity driven variations.

关键词： Systematics Sociology Process control Tail Aerospace electronics Dielectrics Dielectric breakdown

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A Physical Unclonable Function Leveraging Hot Carrier Injection Aging

A Physical Unclonable Function Leveraging Hot Carrier Inject...

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Annual International Symposium on reliability Physics

作者： Rachael J. Parker Jyothi Bhaskarr A. Velamala Kuan-Yueh James Shen David Johnston Yao-Feng Chang Stephen M. Ramey Siang-Jhih Sean Wu Padma Penmatsa Design Engineering Group Intel Corporation Hillsboro OR U.S.A Logic Technology Development Quality & Reliability Intel Corporation Hillsboro OR U.S.A Manufacturing and Product Engineering Intel Corporation Folsom CA U.S.A

Physical Unclonable Functions (PUFs) are low-cost cryptographic primitives used to generate unique, secure, and stable IDs for device authentication and secure communication. PUFs rely on process variation inherent in the manufacturing flow making it impossible to predict or clone chip IDs providing a high level of security and tamper resistance. A commonly studied PUF is the memory PUF which suffers high Bit Error Rate (BER) across environmental conditions. This paper introduces a novel NFET PUF featuring a Hot Carrier Injection (HCI) stress mechanism to lower BER to near zero. Post-Si data from a lkb PUF array fabricated in Intel4 FinFET technology is presented in comparison to a hybrid-SRAM style PUF. BER results were studied with different stress parameters enabling manufacturing flow for HCI based PUFs.

关键词： Human computer interaction Bit error rate Hot carrier injection Physical unclonable function FinFETs Silicon Manufacturing

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Novel Re-configurable Circuits For Aging Characterization: Connecting Devices to Circuits

Novel Re-configurable Circuits For Aging Characterization: C...

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Annual International Symposium on reliability Physics

作者： Ketul B. Sutaria Jihan Standfest Inanc Meric Amirhossein H. Davoody Swaroop Kumar Namalapuri T. Mutyala Supriya P. Balkaran Gill Stephen Ramey Jeffery Hicks Logic Technology Development Quality and Reliability Hillsboro Oregon

ISBN: (数字)9781728131993

ISBN: (纸本)9781728132006

Circuit reliability is a significant concern in scaled technologies. Physical aging models derived by DC stress on discrete devices are accurate to an extent, but can be further improved by evaluating the behaviour of simple circuits such as ring oscillators (RO). In this work, we establish correlation between individual device degradation to circuit's figure of merit (frequency degradation) to refine understanding of the predictive ability of DC models. We further present novel re-configurable circuits that enables different waveform scenarios seen in design to bridge gaps between DC-stressed device aging and complex circuits. Unique features of this work include: (1) Correlating discrete device degradation to circuit performance degradation, (2) development of a novel PMOS/NMOS aging isolator circuit (PNI) which can isolate the aging contribution of a single device type, and (3) development of a state-of-art re-configurable circuit that modulate waveforms to customize the aging contribution from any particular physical mechanism (NBTI, PBTI, N-HCI or P-HCI).

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Modeling Framework for Transistor Aging Playback in Advanced technology Nodes

Modeling Framework for Transistor Aging Playback in Advanced...

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Annual International Symposium on reliability Physics

作者： I. Meric S. Ramey S. Novak S. Gupta S. P. Mudanai J. Hicks Logic Technology Development Quality and Reliability Pre-Silicon Quality and Reliability Logic Technology Development Advanced Design Intel Co Hillsboro Oregon U.S.A

ISBN: (数字)9781728131993

ISBN: (纸本)9781728132006

With continuous channel length scaling and ongoing demand for higher operating frequencies, HCI degradation and combining BTI and HCI aging mechanisms in compact aging models becomes important for accurately capturing end-of-life circuit behavior. We have developed an aging playback model that can replay aged transistor I-V characteristics over a large bias range including both mechanisms. The model uses the transistor VT shift, mobility degradation, and a localization coefficient to combine the impact of individual BTI and HCI components. It can be used for both NMOS and PMOS, as well as logic and I/O devices and is part of Intel process design kits.

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On the Correlation of Laser-induced and High-Energy Proton Beam-induced Single Event Latchup

On the Correlation of Laser-induced and High-Energy Proton B...

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Annual International Symposium on reliability Physics

作者： Bahar Ajdari Samwel Sekwao Ricardo Ascazubi Adam Neale Norbert Seifert Product Reliability Services Corporate Quality Network Intel Corporation Hillsboro OR Logic Technology Development Q&R Corporate Quality Network Intel Corporation Hillsboro OR 97124

ISBN: (数字)9781728131993

ISBN: (纸本)9781728132006

We report on pulsed laser and high-energy proton induced Single Event Latchup (SEL) testing. Arrayed Silicon Controlled Rectifier (SCR) structures that implement various different layout design styles relevant to SEL have been designed and fabricated to make them accessible to both laser and beam testing. Our results demonstrate a qualitative but not quantitative correlation of laser- and beam-induced SEL threshold voltages and cross sections. Therefore, for a complete understanding of SEL sensitivities, pulsed laser injection remains a complementary technique.

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Silicon reliability Characterization of Intel’s Foveros 3D Integration technology for logic-on-logic Die Stacking

Silicon Reliability Characterization of Intel’s Foveros 3D ...

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Annual International Symposium on reliability Physics

作者： Chetan Prasad Sunny Chugh Hannes Greve I-chen Ho Enamul Kabir Cheyun Lin Mahjabin Maksud Steven R. Novak Benjamin Orr Keun Woo Park Anthony Schmitz Zhizheng Zhang Peng Bai Doug B. Ingerly Emre Armagan Hsinwei Wu Patrick Stover Lance Hibbeler Michael O’Day Daniel Pantuso Logic Technology Development Quality and Reliability Intel Corporation Hillsboro OR U.S.A. Logic Technology Development Intel Corporation Hillsboro OR U.S.A. Assembly Test Technology Development Quality and Reliability Intel Corporation Chandler AZ U.S.A. Assembly Test Technology Development Intel Corporation Chandler AZ U.S.A. Technology Computed Aided Design Intel Corporation Hillsboro OR U.S.A.

ISBN: (数字)9781728131993

ISBN: (纸本)9781728132006

This work presents silicon reliability characterization of Intel's Foveros three-dimensional (3D) logic-on-logic stacking technology implemented on the 22FFL process node. Simulations and data demonstrate mechanical strain safe zones around Through Silicon Vias (TSVs). Evaluations of TSV impact on transistor, interconnect, and defect reliability are reported with a Si technology focus. TSV and bump architectures pass thermomechanical assessments on the final optimized process flow. Foveros 3D stacking technology is shown to exhibit robust silicon reliability.

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