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Impact of interfacial chemistry on adhesion and electromigration in Cu interconnects

Impact of interfacial chemistry on adhesion and electromigra...

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Advanced Metallization Conference 2004, AMC 2004

作者： Zhou, Ying Scherban, Tracey Xu, Guanghai He, Jun Miner, Barbara Jan, Chia-Hong Ott, Andrew O'Loughlin, Jennifer Ingerly, Doug Leu, Jihperng Technology Development Quality and Reliability Logic Technology Development Intel Corporation Hillsboro OR 97124 Portland Technology Development Logic Technology Development Intel Corporation Hillsboro OR 97124

The impact of etch-stop (ES)/Cu interfacial chemistry on adhesion and electromigration (EM) has been systematically investigated by varying Cu surface chemistry, etch-stop film chemistry, metal capping layers, and thermal annealing conditions. Adhesion and EM improvement directly correlate with reducing interfacial oxygen for all the systems studied. While the adhesion of freshly deposited ES films strongly depends on the Cu surface chemistry and ES deposition conditions, the hermeticity of the ES film significantly impacts the film and interface chemistry during subsequent processing and thermal cycles, consequently affecting the long term stability of adhesion and electromigration performance. The mechanism for the correlation and material properties governing the interfacial chemistry will be discussed. © 2005 Materials Research Society.

关键词： Copper

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A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects 63

A 10nm high performance and low-power CMOS technology featur...

引用

63rd IEEE International Electron Devices Meeting, IEDM 2017

作者： Auth, C. Aliyarukunju, A. Asoro, M. Bergstrom, D. Bhagwat, V. Birdsall, J. Bisnik, N. Buehler, M. Chikarmane, V. Ding, G. Fu, Q. Gomez, H. Han, W. Hanken, D. Haran, M. Hattendorf, M. Heussner, R. Hiramatsu, H. Ho, B. Jaloviar, S. Jin, I. Joshi, S. Kirby, S. Kosaraju, S. Kothari, H. Leatherman, G. Lee, K. Leib, J. Madhavan, A. Maria, K. Meyer, H. Mule, T. Parker, C. Parthasarathy, S. Pelto, C. Pipes, L. Post, I. Prince, M. Rahman, A. Rajamani, S. Saha, A. Dacuna Santos, J. Sharma, M. Sharma, V. Shin, J. Sinha, P. Smith, P. Sprinkle, M. Amour, A.St. Staus, C. Suri, R. Towner, D. Tripathi, A. Tura, A. Ward, C. Yeoh, A. Logic Technology Development United States Quality and Reliability Engineering Intel Corporation United States

ISBN: (纸本)9781538635599

A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local interconnect layers is described. For high density, a novel self-aligned contact over active gate process and elimination of the dummy gate at cell boundaries are introduced. The transistors feature rectangular fins with 7nm fin width and 46nm fin height, 5th generation high-k metal gate, and 7th-generation strained silicon. Four or six workfunction metal stacks are used to enable undoped fins for low Vt, standard Vt and optional high Vt devices. Interconnects feature 12 metal layers with ultra-low-k dielectrics throughout the interconnect stack. The highest drive currents with the highest cell densities are reported for a 10nm technology. © 2017 IEEE.

关键词： FinFET

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A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171m2 SRAM cell size in a 291Mb array

A 32nm logic technology featuring 2nd-generation high-k + me...

引用

2008 IEEE International Electron Devices Meeting, IEDM 2008

作者： Natarajan, S. Armstrong, M. Bost, M. Brain, R. Brazier, M. Chang, C.-H. Chikarmane, V. Childs, M. Deshpande, H. Dev, K. Ding, G. Ghani, T. Golonzka, O. Han, W. He, J. Heussner, R. James, R. Jin, I. Kenyon, C. Klopcic, S. Lee, S.-H. Liu, M. Lodha, S. McFadden, B. Murthy, A. Neiberg, L. Neirynck, J. Packan, P. Pae, S. Parker, C. Pelto, C. Pipes, L. Sebastian, J. Seiple, J. Sell, B. Sivakumar, S. Song, B. Tone, K. Troeger, T. Weber, C. Yang, M. Yeoh, A. Zhang, K. Logic Technology Development United States Quality and Reliability Engineering United States TCAD Intel Corporation United States

ISBN: (纸本)9781424423781

A 32nm generation logic technology is described incorporating 2 nd-generation high-k + metal-gate technology, 193nm immersion lithography for critical patterning layers, and enhanced channel strain techniques. The transistors feature 9Å EOT high-k gate dielectric, dual band-edge workfunction metal gates, and 4th-generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. Process yield, performance and reliability are demonstrated on a 291 Mbit SRAM test vehicle, with 0.171 μm2 cell size, containing >1.9 billion transistors.

关键词： Computer circuits

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reliability for manufacturing on 45nm logic technology with high-k + metal gate transistors and Pb-free packaging

Reliability for manufacturing on 45nm logic technology with ...

引用

2009 IEEE International reliability Physics Symposium, IRPS 2009

作者： Kasim, Rahim Connor, Chris Hicks, Jeff Jopling, Jason Litteken, Chris Logic Technology Development Quality and Reliability Intel Corporation 5200 N.E. ElamYoung Pkwy Hillsboro OR 97124 United States

ISBN: (纸本)0780388038

This paper addresses several key aspects of integrated reliability for the Intel 45nm logic technology with high-K metal gate (HK+MG) transistors and Pb-free packaging. Significant changes in process architecture and materials were introduced and careful integration and manufacturing innovations were needed to meet historical expectations for transistor, defect, and package reliability. Furthermore the stability of intrinsic and defect reliability performance needed to be demonstrated. Highly accelerated TDDB and bias temperature instability (BTI) tests were implemented to enable very high sampling rates, establishing stable transistor reliability in high manufacturing volumes. Integrated product defect reliability results are presented showing that the historical correlation to yield defect density for stable manufacturing processes is maintained on this generation into an even lower fail rate regime. Similarly, volume package reliability monitor data are shown validating thermo-mechanical stability of the 1st level Pb-free package interconnect. ©2009 IEEE.

关键词： Transistors

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Novel Re-configurable Circuits For Aging Characterization: Connecting Devices to Circuits

Novel Re-configurable Circuits For Aging Characterization: C...

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Annual International Symposium on reliability Physics

作者： Ketul B. Sutaria Jihan Standfest Inanc Meric Amirhossein H. Davoody Swaroop Kumar Namalapuri T. Mutyala Supriya P. Balkaran Gill Stephen Ramey Jeffery Hicks Logic Technology Development Quality and Reliability Hillsboro Oregon

ISBN: (数字)9781728131993

ISBN: (纸本)9781728132006

Circuit reliability is a significant concern in scaled technologies. Physical aging models derived by DC stress on discrete devices are accurate to an extent, but can be further improved by evaluating the behaviour of simple circuits such as ring oscillators (RO). In this work, we establish correlation between individual device degradation to circuit's figure of merit (frequency degradation) to refine understanding of the predictive ability of DC models. We further present novel re-configurable circuits that enables different waveform scenarios seen in design to bridge gaps between DC-stressed device aging and complex circuits. Unique features of this work include: (1) Correlating discrete device degradation to circuit performance degradation, (2) development of a novel PMOS/NMOS aging isolator circuit (PNI) which can isolate the aging contribution of a single device type, and (3) development of a state-of-art re-configurable circuit that modulate waveforms to customize the aging contribution from any particular physical mechanism (NBTI, PBTI, N-HCI or P-HCI).

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Modeling Framework for Transistor Aging Playback in Advanced technology Nodes

Modeling Framework for Transistor Aging Playback in Advanced...

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Annual International Symposium on reliability Physics

作者： I. Meric S. Ramey S. Novak S. Gupta S. P. Mudanai J. Hicks Logic Technology Development Quality and Reliability Pre-Silicon Quality and Reliability Logic Technology Development Advanced Design Intel Co Hillsboro Oregon U.S.A

ISBN: (数字)9781728131993

ISBN: (纸本)9781728132006

With continuous channel length scaling and ongoing demand for higher operating frequencies, HCI degradation and combining BTI and HCI aging mechanisms in compact aging models becomes important for accurately capturing end-of-life circuit behavior. We have developed an aging playback model that can replay aged transistor I-V characteristics over a large bias range including both mechanisms. The model uses the transistor VT shift, mobility degradation, and a localization coefficient to combine the impact of individual BTI and HCI components. It can be used for both NMOS and PMOS, as well as logic and I/O devices and is part of Intel process design kits.

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Practical implications of chip-level statistical electromigration

Practical implications of chip-level statistical electromigr...

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Annual International Symposium on reliability Physics

作者： Anthony Schmitz Logic Technology Development Quality and Reliability Intel Corporation Hillsboro OR USA

The accurate setting of electromigration (EM) design guidelines early is necessary to achieve chip-level fail goals. The issue is even more critical with the recognition of the percentage fail as a stochastic issue based on the individual EM elements. The challenge is the degree to fix those elements prior to the knowledge of chip-level fail rate. This paper will demonstrate a test case and approaches to early design guidelines which have shown success at meeting chip-level EM fail goals.

关键词： Electromigration reliability engineering Current density Temperature sensors Junctions Guidelines

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reliability for manufacturing on 45nm logic technology with high-k + metal gate transistors and Pb-free packaging

Reliability for manufacturing on 45nm logic technology with ...

引用

Annual International Symposium on reliability Physics

作者： Rahim Kasim Chris Connor Jeff Hicks Jason Jopling Chris Litteken Logic Technology Development Quality and Reliability Intel Corporation Hillsboro OR USA

This paper addresses several key aspects of integrated reliability for the Intel 45 nm logic technology with high-K metal gate (HK + MG) transistors and Pb-free packaging. Significant changes in process architecture and materials were introduced and careful integration and manufacturing innovations were needed to meet historical expectations for transistor, defect, and package reliability. Furthermore the stability of intrinsic and defect reliability performance needed to be demonstrated. Highly accelerated TDDB and bias temperature instability (BTI) tests were implemented to enable very high sampling rates, establishing stable transistor reliability in high manufacturing volumes. Integrated product defect reliability results are presented showing that the historical correlation to yield defect density for stable manufacturing processes is maintained on this generation into an even lower fail rate regime. Similarly, volume package reliability monitor data are shown validating thermo-mechanical stability of the 1st level Pb-free package interconnect.

关键词： logic High K dielectric materials High-K gate dielectrics Packaging Manufacturing processes Technological innovation Materials reliability Stability Life estimation Temperature

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Susceptibility of planar and 3D tri-gate technologies to muon-induced single event upsets

Susceptibility of planar and 3D tri-gate technologies to muo...

引用

Annual International Symposium on reliability Physics

作者： Norbert Seifert Shah Jahinuzzaman Jyothi Velamala Nikunj Patel Logic Technology Development Quality and Reliability Intel Corporation Hillsboro OR USA

We report on muon-induced single event upsets (SEU) in SRAMs built on 32nm planar and 22nm and 14nm 3D Tri-Gate technologies. Experimental cross sections were measured using the M20C positive muon beamline at TRIUMF. Physics-based simulations were conducted to estimate sea-level SEU rates for both, positive and negative muons. Our results indicate that the muon induced upset rate is negligible compared to neutron induced upset rate, and the introduction of 3D Tri-Gate transistors reduced the susceptibility to muons by approximately two orders of magnitude relative to 32nm planar cross sections.

关键词： Mesons Neutrons Particle beams Life estimation Random access memory Acceleration Atmospheric modeling

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A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array

A 32nm logic technology featuring 2nd-generation high-k + me...

引用

International Electron Devices Meeting (IEDM)

作者： S. Natarajan M. Armstrong M. Bost R. Brain M. Brazier C.-H. Chang V. Chikarmane M. Childs H. Deshpande K. Dev G. Ding T. Ghani O. Golonzka W. Han J. He R. Heussner R. James I. Jin C. Kenyon S. Klopcic S.-H. Lee M. Liu S. Lodha B. McFadden A. Murthy L. Neiberg J. Neirynck P. Packan S. Pae C. Parker C. Pelto L. Pipes J. Sebastian J. Seiple B. Sell S. Sivakumar B. Song K. Tone T. Troeger C. Weber M. Yang A. Yeoh K. Zhang Logic Technology Development Quality and Reliability Engineering TCAD Intel Corporation

A 32 nm generation logic technology is described incorporating 2 nd -generation high-k + metal-gate technology, 193 nm immersion lithography for critical patterning layers, and enhanced channel strain techniques. The transistors feature 9 Aring EOT high-k gate dielectric, dual band-edge workfunction metal gates, and 4 th -generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. Process yield, performance and reliability are demonstrated on a 291 Mbit SRAM test vehicle, with 0.171 mum 2 cell size, containing >1.9 billion transistors.

关键词： logic High K dielectric materials High-K gate dielectrics Lithography Capacitive sensors Silicon MOS devices Random access memory Testing Vehicles

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