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检索条件"机构=Logic Technology Development Quality and Reliability"

共 48 条记录，以下是11-20 订阅

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reliability Characterization for 12 V Application Using the 22FFL FinFET technology

Reliability Characterization for 12 V Application Using the ...

引用

Annual International Symposium on reliability Physics

作者： C.-Y. Su M. Armstrong S. Chugh M. El-tanani H. Greve H. Li M. Maksud B. Orr C. Perini J. Palmer L. Paulson S. Ramey J. Waldemer Y. Yang D. Young Logic Technology Development Quality and Reliability Intel Corp. Hillsboro Oregon U.S.A. Portland Technology Development Department Intel Corp. Hillsboro Oregon U.S.A. Device Development Group Intel Corp. Hillsboro Oregon U.S.A.

ISBN: (数字)9781728131993

ISBN: (纸本)9781728132006

The 22FFL technology developed for operation to 3.3V is used to investigate process and design considerations required to extend technology capability to 12 V applications. A prototype chip was carefully designed in close consideration with the technology reliability requirements of the lower voltage components to demonstrate product-level reliability capabilities. The reliability of components such as transistors, well junctions, back-end dielectrics and MIMCAPs is thoroughly characterized and proven robust throughout a 10-year lifetime. The results demonstrate a reliable technology capability that is compliant with industrial standards to enable high-voltage design requirements.

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Implementation of High Power RF Devices with Hybrid Workfunction and OxideThickness in 22nm Low-Power FinFET technology

Implementation of High Power RF Devices with Hybrid Workfunc...

引用

International Electron Devices Meeting (IEDM)

作者： H.-J. Lee S. Morarka S. Rami Q. Yu M. Weiss G. Liu M. Armstrong C. - Y. Su D. Ali B. Sell Y. Zhang Logic Technology Development Intel Corporation Hillsboro Oregon USA Quality and Reliability Intel Corporation Hillsboro Oregon USA

Unique High-Power FinFET device with multiple workfunction materials and oxide thickness under a common gate, dubbed as HyPowerFF, is introduced. The proposed devices are as reliable as high-voltage IO devices with up to 7.1V of breakdown voltage and provide 290GHz of f max suitable for power-efficient RF power-amplifier (PA) design.

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A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects 63

A 10nm high performance and low-power CMOS technology featur...

引用

63rd IEEE International Electron Devices Meeting, IEDM 2017

作者： Auth, C. Aliyarukunju, A. Asoro, M. Bergstrom, D. Bhagwat, V. Birdsall, J. Bisnik, N. Buehler, M. Chikarmane, V. Ding, G. Fu, Q. Gomez, H. Han, W. Hanken, D. Haran, M. Hattendorf, M. Heussner, R. Hiramatsu, H. Ho, B. Jaloviar, S. Jin, I. Joshi, S. Kirby, S. Kosaraju, S. Kothari, H. Leatherman, G. Lee, K. Leib, J. Madhavan, A. Maria, K. Meyer, H. Mule, T. Parker, C. Parthasarathy, S. Pelto, C. Pipes, L. Post, I. Prince, M. Rahman, A. Rajamani, S. Saha, A. Dacuna Santos, J. Sharma, M. Sharma, V. Shin, J. Sinha, P. Smith, P. Sprinkle, M. Amour, A.St. Staus, C. Suri, R. Towner, D. Tripathi, A. Tura, A. Ward, C. Yeoh, A. Logic Technology Development United States Quality and Reliability Engineering Intel Corporation United States

ISBN: (纸本)9781538635599

A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local interconnect layers is described. For high density, a novel self-aligned contact over active gate process and elimination of the dummy gate at cell boundaries are introduced. The transistors feature rectangular fins with 7nm fin width and 46nm fin height, 5th generation high-k metal gate, and 7th-generation strained silicon. Four or six workfunction metal stacks are used to enable undoped fins for low Vt, standard Vt and optional high Vt devices. Interconnects feature 12 metal layers with ultra-low-k dielectrics throughout the interconnect stack. The highest drive currents with the highest cell densities are reported for a 10nm technology. © 2017 IEEE.

关键词： FinFET

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Transistor reliability characterization and comparisons for a 14 nm tri-gate technology optimized for System-on-Chip and foundry platforms

Transistor reliability characterization and comparisons for ...

引用

Annual International Symposium on reliability Physics

作者： C. Prasad K. W. Park M. Chahal I. Meric S. R. Novak S. Ramey P. Bai H.-Y. Chang N. L. Dias W. M. Hafez C.-H. Jan N. Nidhi R. W. Olac-vaw R. Ramaswamy C. Tsai Logic Technology Development Quality and Reliability Intel Corporation Hillsboro OR U.S.A Portland Technology Development Intel Corporation Hillsboro OR U.S.A

ISBN: (纸本)9781467391382

The transistor reliability characterization of a 14nm System-on-Chip (SoC) node optimized for low power operation is described. In-depth assessments of reliability and performance for Core and I/O devices are performed on logic and SoC nodes, and clear trends with scaling are identified. Insight is provided into hot carrier and off-state aging, and self-heat effects. Technological advancements across process nodes demonstrate the ability to achieve matched or improved reliability in conjunction with robust generational performance gains. The 14nm SoC node is shown to be robust for all transistor reliability modes. Process monitor data are used to demonstrate the stability of the production line in high-volume manufacturing.

关键词： logic gates Transistors MOS devices Dielectrics Integrated circuit reliability Degradation

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Susceptibility of planar and 3D tri-gate technologies to muon-induced single event upsets

Susceptibility of planar and 3D tri-gate technologies to muo...

引用

Annual International Symposium on reliability Physics

作者： Norbert Seifert Shah Jahinuzzaman Jyothi Velamala Nikunj Patel Logic Technology Development Quality and Reliability Intel Corporation Hillsboro OR USA

We report on muon-induced single event upsets (SEU) in SRAMs built on 32nm planar and 22nm and 14nm 3D Tri-Gate technologies. Experimental cross sections were measured using the M20C positive muon beamline at TRIUMF. Physics-based simulations were conducted to estimate sea-level SEU rates for both, positive and negative muons. Our results indicate that the muon induced upset rate is negligible compared to neutron induced upset rate, and the introduction of 3D Tri-Gate transistors reduced the susceptibility to muons by approximately two orders of magnitude relative to 32nm planar cross sections.

关键词： Mesons Neutrons Particle beams Life estimation Random access memory Acceleration Atmospheric modeling

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Transistor aging and reliability in 14nm tri-gate technology

Transistor aging and reliability in 14nm tri-gate technology

引用

Annual International Symposium on reliability Physics

作者： S. Novak C. Parker D. Becher M. Liu M. Agostinelli M. Chahal P. Packan P. Nayak S. Ramey S. Natarajan Logic Technology Development Quality and Reliability Portland Technology Development Intel Corp. Hillsboro Oregon U.S.A.

This paper details the transistor aging and gate oxide reliability of Intel's 14nm process technology. This technology introduces Intel's 2 nd generation tri-gate transistor and the 4 th generation of high-κ dielectrics and metal-gate electrodes. The reliability metrics reported here highlight reliability gains attained through transistor optimizations as well as intrinsic challenges from device scaling.

关键词： Degradation logic gates Transistors Stress Hot carriers Integrated circuit reliability

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Aging model challenges in deeply scaled tri-gate technologies

Aging model challenges in deeply scaled tri-gate technologie...

引用

IEEE International Workshop Integrated reliability

作者： S. Ramey Y. Lu I. Meric S. Mudanai S. Novak C. Prasad J. Hicks Logic Technology Development Quality and Reliability Intel Corp. Hillsboro Oregon U.S.A.

As tri-gate transistor technologies continue to scale to smaller dimensions, a variety of aging mechanisms become important to include in models to accurately predict end-of-life transistor performance. Traditional aging effects such as BTI and hot carrier continue to play a role. However, modeling these mechanisms becomes more complicated with the addition of recovery, variation, and local self-heating. Further, second-order effects are starting to accumulate, such as recovery interactions, minority carrier gate injection, damage localization, and interactions between hot carrier and BTI. This work highlights the roles and impacts of these various effects and how they will need to fit into a comprehensive aging model.

关键词： Aging Degradation logic gates Hot carriers Stress Transistors Integrated circuit modeling

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Transistor reliability variation correlation to threshold voltage

Transistor reliability variation correlation to threshold vo...

引用

Annual International Symposium on reliability Physics

作者： S. Ramey M. Chahal P. Nayak S. Novak C. Prasad J. Hicks Logic Technology Development Quality Reliability Intel Corp. Hillsboro Oregon U.S.A.

MOSFET reliability data are often represented as a function of gate overdrive (V G -V T ) with the implicit assumption that overdrive is the appropriate normalizing parameter. While this can be true for some specific sources of variation, reliability does not necessarily track gate overdrive. This paper explores systematic and random sources of variation in TDDB, BTI, and hot carrier degradation data in Intel's tri-gate technologies. We find that random variation captured within a baseline of reliability data does not, in general, trend with overdrive. However, some sources of systematic variation are correlated or, interestingly, anti-correlated with overdrive.

关键词： logic gates Doping MOS devices Stress Degradation reliability Metals

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A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size

A 14nm logic technology featuring 2nd-generation FinFET, air...

引用

International Electron Devices Meeting (IEDM)

作者： S. Natarajan M. Agostinelli S. Akbar M. Bost A. Bowonder V. Chikarmane S. Chouksey A. Dasgupta K. Fischer Q. Fu T. Ghani M. Giles S. Govindaraju R. Grover W. Han D. Hanken E. Haralson M. Haran M. Heckscher R. Heussner P. Jain R. James R. Jhaveri I. Jin H. Kam E. Karl C. Kenyon M. Liu Y. Luo R. Mehandru S. Morarka L. Neiberg P. Packan A. Paliwal C. Parker P. Patel R. Patel C. Pelto L. Pipes P. Plekhanov M. Prince S. Rajamani J. Sandford B. Sell S. Sivakumar P. Smith B. Song K. Tone T. Troeger J. Wiedemer M. Yang K. Zhang Logic Technology Development Quality and Reliability Engineering DTS Intel Corporation

A 14nm logic technology using 2 nd -generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4 th generation high-k metal gate, and 6 th -generation strained silicon, resulting in the highest drive currents yet reported for 14nm technology. This technology is in high-volume manufacturing.

关键词： Doping logic gates Market research FinFETs Random access memory

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Advanced CMOS reliability challenges

Advanced CMOS reliability challenges

引用

International Symposium on VLSI technology, Systems and Applications

作者： Chetan Prasad Logic Technology Development Quality and Reliability Intel Corporation Hillsboro U.S.A

This work reviews transistors of advanced CMOS process nodes from a reliability perspective and covers some of the important challenges and solutions. Physical mechanisms for various modes are investigated for 65nm to 22nm nodes with focus on disruptive changes such as HK/MG and Tri-gate/FinFET. The importance of modeling non-idealities and variation is also emphasized, and projections are made for scaling to sub-20nm with comparisons to existing research.

关键词： Degradation Optimization logic gates Integrated circuit reliability FinFETs Aging

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