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International reliability Physics Symposium

作者： S. Ramey J. Hicks L. S. Liyanage S. Novak Logic Technology Development Quality and Reliability Intel Corp. Hillsboro Oregon U.S.A.

ISBN: (纸本)9781479933181

BTI recovery in tri-gate devices matches data and model predictions from planar devices, indicating a consistent physical basis for the mechanism and no influence from transistor architecture features such as crystal orientation, confinement, and vertical sidewalls. This consistency enables extending existing models established on planar devices to capture temperature and voltage dependencies of recovery. A new experimental technique allows extraction of an effective activation energy for recovery. The observation of complete recovery demonstrates that no permanent damage occurs during stress.

关键词： 22nm Tri-gate technology model predictions planar devices

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reliability studies of a 22nm SoC platform technology featuring 3-D tri-gate, optimized for ultra low power, high performance and high density application

Reliability studies of a 22nm SoC platform technology featur...

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Annual International Symposium on reliability Physics

作者： A. Rahman P. Bai G. Curello J. Hicks C. -H. Jan M. Jamil J. Park K. Phoa M. S. Rahman C. Tsai B. Woolery J.-Y. Yeh Logic Technology Development Quality & Reliability Intel Corporation Hillsboro OR USA

ISBN: (纸本)9781479901128

Transistor reliability characterization studies are reported for a state of the art 22nm 3-D tri-gate HK/MG SoC technology with logic and HV I/O transistor architecture. TDDB, BTI and HCI degradation modes for logic and I/O transistors are studied and excellent reliability is demonstrated. In order to simultaneously integrate logic and HV 3-D tri-gate transistors with robust reliability, the importance of process optimization is emphasized.

关键词： Transistors logic gates MOS devices reliability System-on-chip Degradation Dielectrics

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Intrinsic transistor reliability improvements from 22nm tri-gate technology

Intrinsic transistor reliability improvements from 22nm tri-...

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Annual International Symposium on reliability Physics

作者： S. Ramey A. Ashutosh C. Auth J. Clifford M. Hattendorf J. Hicks R. James A. Rahman V. Sharma A. St Amour C. Wiegand Logic Technology Development Quality and Reliability Portland Technology Development Intel Corporation Hillsboro OR USA

This paper highlights the intrinsic reliability capabilities of Intel's 22nm process technology, which introduced the tri-gate transistor architecture and features a 3 rd generation high-κ/metal-gate process. Results are detailed from all traditional transistor reliability mechanisms, including BTI, TDDB, SILC, and HCI. In addition, characteristics unique to this transistor architecture and process technology are described.

关键词： logic gates Transistors Integrated circuit reliability MOS devices Degradation Optimization

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Self-heat reliability Considerations on Intel's 22nm Tri-Gate technology

Self-heat Reliability Considerations on Intel's 22nm Tri-Gat...

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IEEE International reliability Physics Symposium

作者： C. Prasad L. Jiang D. Singh M. Agostinelli C. Auth P. Bai T. Eiles J. Hicks C. H. Jan K. Mistry S. Natarajan B. Niu P. Packan D. Pantuso I. Post S. Ramey A. Schmitz B. Sell S. Suthram J. Thomas C. Tsai P. Vandervoorn Logic Teclmology Development Quality and Reliability Intel Corporation Design and Technology Solutions Intel Corporation Portland Technology Development Intel Corporation

This paper describes various measurements on self-heat performed on Intel's 22nm process technology, and outlines its reliability implications. Comparisons to thermal modeling results and analytical data show exce... 详细信息

ISBN: (纸本)9781479901128

关键词： ANALYTICAL DATA thermal model Outlines

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Practical implications of chip-level statistical electromigration

Practical implications of chip-level statistical electromigr...

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Annual International Symposium on reliability Physics

作者： Anthony Schmitz Logic Technology Development Quality and Reliability Intel Corporation Hillsboro OR USA

The accurate setting of electromigration (EM) design guidelines early is necessary to achieve chip-level fail goals. The issue is even more critical with the recognition of the percentage fail as a stochastic issue based on the individual EM elements. The challenge is the degree to fix those elements prior to the knowledge of chip-level fail rate. This paper will demonstrate a test case and approaches to early design guidelines which have shown success at meeting chip-level EM fail goals.

关键词： Electromigration reliability engineering Current density Temperature sensors Junctions Guidelines

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A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

A 22nm high performance and low-power CMOS technology featur...

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2012 Symposium on VLSI technology, VLSIT 2012

作者： Auth, C. Allen, C. Blattner, A. Bergstrom, D. Brazier, M. Bost, M. Buehler, M. Chikarmane, V. Ghani, T. Glassman, T. Grover, R. Han, W. Hanken, D. Hattendorf, M. Hentges, P. Heussner, R. Hicks, J. Ingerly, D. Jain, P. Jaloviar, S. James, R. Jones, D. Jopling, J. Joshi, S. Kenyon, C. Liu, H. McFadden, R. McIntyre, B. Neirynck, J. Parker, C. Pipes, L. Post, I. Pradhan, S. Prince, M. Ramey, S. Reynolds, T. Roesler, J. Sandford, J. Seiple, J. Smith, P. Thomas, C. Towner, D. Troeger, T. Weber, C. Yashar, P. Zawadzki, K. Mistry, K. Logic Technology Development Intel Corp. Hillsboro OR United States Quality and Reliability Engineering Intel Corp. Hillsboro OR United States TCAD Intel Corp. Hillsboro OR United States

ISBN: (纸本)9781467308458

A 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time. These transistors feature a 3rd-generation high-k + metal-gate technology and a 5 th generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS. The use of tri-gate transistors provides steep subthreshold slopes (∼70mV/dec) and very low DIBL (∼50mV/V). Self-aligned contacts are implemented to eliminate restrictive contact to gate registration requirements. Interconnects feature 9 metal layers with ultra-low-k dielectrics throughout the interconnect stack. High density MIM capacitors using a hafnium based high-k dielectric are provided. The technology is in high volume manufacturing. © 2012 IEEE.

关键词： High-k dielectric

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reliability studies of a 32nm System-on-Chip (SoC) platform technology with 2nd generation high-k/metal gate transistors

Reliability studies of a 32nm System-on-Chip (SoC) platform ...

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Annual International Symposium on reliability Physics

作者： A. Rahman M. Agostinelli P. Bai G. Curello H. Deshpande W. Hafez C. -H. Jan K. Komeyli J. Park K. Phoa C. Tsai J.-Y. Yeh J. Xu Logic Technology Development Quality & Reliability Intel Corporation Hillsboro OR USA Logic Technology Development Intel Corporation Hillsboro OR USA

Extensive reliability characterization of a state of the art 32nm strained HK/MG SoC technology with triple transistor architecture is presented here. BTI, HCI and TDDB degradation modes on the logic and I/O (1.2V, 1.8V and 3.3V tolerant) transistors are studied and excellent reliability is demonstrated. Importance of process optimizations to integrate robust I/O transistors without degrading performance and reliability of logic transistors emphasized. Finally, Intrinsic and defect reliability monitoring for HVM are addressed.

关键词： MOS devices Dielectrics logic gates Integrated circuit reliability Transistors Degradation

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Characterization and challenge of TDDB reliability in Cu/low K dielectric interconnect

Characterization and challenge of TDDB reliability in Cu/low...

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Annual International Symposium on reliability Physics

作者： Feng Xia Jun He Prad Prabhumirashi Anthony Schmitz Anthony Lowrie Jeff Hicks Yuriy Shusterman Ruth Brain Intel Corporation Limited Quality and Reliability Hillsboro OR USA Logic Technology Development Hillsboro OR USA

Interconnect dielectric reliability challenges increase every generation due to dimension scaling and pursuing of lower K dielectrics for performance. In this paper, TDDB reliability characteration, process innovation, process control and product validation are presented based on Intel 32 nm technology node. In definition and technology development phase, extensive characterization and process innovation are needed to enable the proper choices of materials and processes. For any given healthy process and material set, the TDDB reliability is determined by via to line and line to line space distribution, and dominated by the tail distribution of dies with small space. Although different TDDB physical models such as E, root E or other models will project very different failure probability when extrapolating from high Efield to low Efield for the main population, the choice of models makes little difference for product level failure probability from the tail population because the Efield is already in the range of that used for accelerated stressing. Since product failure rate is dominated by tail population, more focus has been given to this area in terms of process development and control. Novel self-aligned via patterning process has been developed for 32 nm technology and significantly improved via to line space and thus the low K TDDB performance. In addition, to ensure superior quality and reliability, extensive process window and product level validation through extended life test are necessary to capture and eliminate worse case process and product corners. A scaling trend and potential path to enable continuing scaling are highlighted.

关键词： reliability Dielectrics Process control Copper Aerospace electronics Technological innovation

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Nanoindentation and Tensile Behavior of Copper Films

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MRS Online Proceedings Library (OPL) 2011年第1期778卷 U4.3-U4.3页

作者： D. Read R. Geiss J. Ramsey T. Scherban G. Xu J. Blaine B. Miner R.D. Emery National Institute of Standards and Technology Boulder CO 80305 Reed College Portland OR 97202 Logic Technology Development Quality & Reliability Intel Corp. Hillsboro OR 97124 Components Research Intel Corp. Chandler AZ 85226

The mechanical properties of ~ 10 mm thick electroplated copper films were investigated by both nanoindentation of supported films and microtensile testing of free-standing films. By utilizing both techniques to examine the same films, the results could be directly compared to one another. Nanoindentation yield strength was found to be 5 – 15 % lower than in the microtensile case. Differences were attributed to grain size differences and, for annealed films, the presence of internal stresses in supported films only. Data from both techniques generally followed the Hall-Petch trend.

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reliability studies on a 45nm low power system-on-chip (SoC) dual gate oxide high-k / metal gate (DG HK+MG) technology

Reliability studies on a 45nm low power system-on-chip (SoC)...

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Annual International Symposium on reliability Physics

作者： C. Prasad P. Bai S. Gannavaram W. Hafez J. Hicks C.-H. Jan J. Lin M. Jones K. Komeyli R. Kotlyar K. Mistry I. Post C. Tsai Logic Technology Development Quality and Reliability Hillsboro OR USA Logic Technology Development Hillsboro OR USA Design and Technology Solutions Intel Corporation Limited Hillsboro OR USA

ISBN: (纸本)9781424454303;9781424454310

In this paper, we present extensive reliability characterization results for a novel dual gate 45 nm HK+MG technology. BTI, HCI and TDDB degradation modes on the logic and I/O transistors are studied and excellent reliability is demonstrated. Emphasis is placed on the importance of process optimizations to support robust I/O transistors while maintaining the high performance and reliability of logic transistors. Monitoring of reliability for HVM and collateral reliability are also addressed.

关键词： Power system reliability High K dielectric materials High-K gate dielectrics Degradation logic MOS devices CMOS technology Robustness Niobium compounds Titanium compounds

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