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reliability for manufacturing on 45nm logic technology with high-k + metal gate transistors and Pb-free packaging

Reliability for manufacturing on 45nm logic technology with ...

引用

2009 IEEE International reliability Physics Symposium, IRPS 2009

作者： Kasim, Rahim Connor, Chris Hicks, Jeff Jopling, Jason Litteken, Chris Logic Technology Development Quality and Reliability Intel Corporation 5200 N.E. ElamYoung Pkwy Hillsboro OR 97124 United States

ISBN: (纸本)0780388038

This paper addresses several key aspects of integrated reliability for the Intel 45nm logic technology with high-K metal gate (HK+MG) transistors and Pb-free packaging. Significant changes in process architecture and materials were introduced and careful integration and manufacturing innovations were needed to meet historical expectations for transistor, defect, and package reliability. Furthermore the stability of intrinsic and defect reliability performance needed to be demonstrated. Highly accelerated TDDB and bias temperature instability (BTI) tests were implemented to enable very high sampling rates, establishing stable transistor reliability in high manufacturing volumes. Integrated product defect reliability results are presented showing that the historical correlation to yield defect density for stable manufacturing processes is maintained on this generation into an even lower fail rate regime. Similarly, volume package reliability monitor data are shown validating thermo-mechanical stability of the 1st level Pb-free package interconnect. ©2009 IEEE.

关键词： Transistors

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reliability for manufacturing on 45nm logic technology with high-k + metal gate transistors and Pb-free packaging

Reliability for manufacturing on 45nm logic technology with ...

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Annual International Symposium on reliability Physics

作者： Rahim Kasim Chris Connor Jeff Hicks Jason Jopling Chris Litteken Logic Technology Development Quality and Reliability Intel Corporation Hillsboro OR USA

This paper addresses several key aspects of integrated reliability for the Intel 45 nm logic technology with high-K metal gate (HK + MG) transistors and Pb-free packaging. Significant changes in process architecture and materials were introduced and careful integration and manufacturing innovations were needed to meet historical expectations for transistor, defect, and package reliability. Furthermore the stability of intrinsic and defect reliability performance needed to be demonstrated. Highly accelerated TDDB and bias temperature instability (BTI) tests were implemented to enable very high sampling rates, establishing stable transistor reliability in high manufacturing volumes. Integrated product defect reliability results are presented showing that the historical correlation to yield defect density for stable manufacturing processes is maintained on this generation into an even lower fail rate regime. Similarly, volume package reliability monitor data are shown validating thermo-mechanical stability of the 1st level Pb-free package interconnect.

关键词： logic High K dielectric materials High-K gate dielectrics Packaging Manufacturing processes Technological innovation Materials reliability Stability Life estimation Temperature

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Low-k interconnect stack with a novel self-aligned via patterning process for 32nm high volume manufacturing

Low-k interconnect stack with a novel self-aligned via patte...

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IEEE International Conference on Interconnect technology

作者： R. Brain S. Agrawal D. Becher R. Bigwood M. Buehler V. Chikarmane M. Childs J. Choi S. Daviess C. Ganpule J. He P. Hentges I. Jin S. Klopcic G. Malyavantham B. McFadden J. Neulinger J. Neirynck Y. Neirynck C. Pelto P. Plekhanov Y. Shusterman T. Van M. Weiss S. Williams F. Xia P. Yashar A. Yeoh Logic Technology Development Hillsboro OR USA Quality & Reliability Intel Corporation Hillsboro OR USA

Interconnect process features are described for a 32 nm high performance logic technology. Lower-k, yet highly manufacturable, carbon-doped oxide (CDO) dielectric layers are introduced on this technology at three layers to address the demand for ever lower metal line capacitance. The pitches have been aggressively scaled to meet the expectation for density, and the metal resistance and electromigration performance have been carefully balanced to meet the high reliability requirements while maintaining the lowest possible resistance. A new patterning scheme has been used to limit any patterning damage to the lower-k ILD and address the increasingly difficult problem of via-to-metal shorting at these very tight pitches. The interconnect stack has a thick metal-9 layer to provide a low resistance path for the power and I/O routing that has been carefully scaled to maintain a low resistance. The combined interconnect stack provides high density, performance, and reliability, and supports a Pb-free 32 nm process.

关键词： Manufacturing processes Routing Capacitance Electromigration Maintenance Current density Dielectric materials Inorganic materials logic devices Power systems

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Frequency and recovery effects in high-κ BTI degradation

Frequency and recovery effects in high-κ BTI degradation

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Annual International Symposium on reliability Physics

作者： Stephen Ramey Chetan Prasad Marty Agostinelli Sangwoo Pae Steven Walstra Satrajit Gupta Jeffrey Hicks Logic and Technology Development Quality and Reliability Intel Corporation Hillsboro OR USA Design Technology Solutions Intel Corporation Hillsboro OR USA

Net end-of-life aging prediction under realistic use conditions is the key objective for any product aging model. In this paper, a net degradation model is introduced and effects such as recovery, subsequent degradation, frequency, duty cycle, and recovery bias are evaluated. The high-kappa recovery behavior observed is consistent with SiO 2 gate stacks, which allows the use of SiO 2 models to predict recovery in both NMOS and PMOS high-kappa transistors.

关键词： Frequency Degradation MOSFETs Stress measurement Voltage Aging Predictive models Inverters MOS devices CMOS logic circuits

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High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors

High performance 32nm logic technology featuring 2nd generat...

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International Electron Devices Meeting (IEDM)

作者： P. Packan S. Akbar M. Armstrong D. Bergstrom M. Brazier H. Deshpande K. Dev G. Ding T. Ghani O. Golonzka W. Han J. He R. Heussner R. James J. Jopling C. Kenyon S-H. Lee M. Liu S. Lodha B. Mattis A. Murthy L. Neiberg J. Neirynck S. Pae C. Parker L. Pipes J. Sebastian J. Seiple B. Sell A. Sharma S. Sivakumar B. Song A. St. Amour K. Tone T. Troeger C. Weber K. Zhang Y. Luo S. Natarajan Logic Technology Development Intel Corporation Hillsboro OR USA Quality and Reliability Engineering Intel Corporation Hillsboro OR USA TCAD Intel Corporation. Intel Corporation Hillsboro OR USA

A 32 nm logic technology for high performance microprocessors is described. 2 nd generation high-k + metal gate transistors provide record drive currents at the tightest gate pitch reported for any 32 nm or 28 nm logic technology. NMOS drive currents are 1.62 mA/um Idsat and 0.231 mA/um Idlin at 1.0 V and 100 nA/um I off . PMOS drive currents are 1.37 mA/um Idsat and 0.240 mA/um Idlin at 1.0 V and 100 nA/um I off . The impact of SRAM cell and array size on Vccmin is reported.

关键词： logic MOS devices Capacitive sensors High K dielectric materials High-K gate dielectrics Moore's Law Silicon Helium reliability engineering Electronic mail

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High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors

High performance 32nm logic technology featuring 2nd generat...

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2009 International Electron Devices Meeting, IEDM 2009

作者： Packan, P. Akbar, S. Armstrong, M. Bergstrom, D. Brazier, M. Deshpande, H. Dev, K. Ding, G. Ghani, T. Golonzka, O. Han, W. He, J. Heussner, R. James, R. Jopling, J. Kenyon, C. Lee, S-H. Liu, M. Lodha, S. Mattis, B. Murthy, A. Neiberg, L. Neirynck, J. Pae, S. Parker, C. Pipes, L. Sebastian, J. Seiple, J. Sell, A. Sharma, A. Sivakumar, S. Song, B. Amour, A.St. Tone, K. Troeger, T. Weber, C. Zhang, K. Luo, Y. Natarajan, S. Logic Technology Development Intel Corporation RA3-353 2501 NW 229th Ave. Hillsboro OR 97124 United States Quality and Reliability Engineering Intel Corporation RA3-353 2501 NW 229th Ave. Hillsboro OR 97124 United States TCAD Intel Corporation. RA3-353 2501 NW 229th Ave. Hillsboro OR 97124 United States

ISBN: (纸本)9781424456406

A 32nm logic technology for high performance microprocessors is described. 2nd generation high-k + metal gate transistors provide record drive currents at the tightest gate pitch reported for any 32nm or 28nm logic technology. NMOS drive currents are 1.62mA/um Idsat and 0.231mA/um Idlin at 1.0V and 100nA/um Ioff. PMOS drive currents are 1.37mA/um Idsat and 0.240mA/um Idlin at 1.0V and 100nA/um Ioff. The impact of SRAM cell and array size on Vccmin is reported. © 2009 IEEE.

关键词： Computer circuits

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A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171m2 SRAM cell size in a 291Mb array

A 32nm logic technology featuring 2nd-generation high-k + me...

引用

2008 IEEE International Electron Devices Meeting, IEDM 2008

作者： Natarajan, S. Armstrong, M. Bost, M. Brain, R. Brazier, M. Chang, C.-H. Chikarmane, V. Childs, M. Deshpande, H. Dev, K. Ding, G. Ghani, T. Golonzka, O. Han, W. He, J. Heussner, R. James, R. Jin, I. Kenyon, C. Klopcic, S. Lee, S.-H. Liu, M. Lodha, S. McFadden, B. Murthy, A. Neiberg, L. Neirynck, J. Packan, P. Pae, S. Parker, C. Pelto, C. Pipes, L. Sebastian, J. Seiple, J. Sell, B. Sivakumar, S. Song, B. Tone, K. Troeger, T. Weber, C. Yang, M. Yeoh, A. Zhang, K. Logic Technology Development United States Quality and Reliability Engineering United States TCAD Intel Corporation United States

ISBN: (纸本)9781424423781

A 32nm generation logic technology is described incorporating 2 nd-generation high-k + metal-gate technology, 193nm immersion lithography for critical patterning layers, and enhanced channel strain techniques. The transistors feature 9Å EOT high-k gate dielectric, dual band-edge workfunction metal gates, and 4th-generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. Process yield, performance and reliability are demonstrated on a 291 Mbit SRAM test vehicle, with 0.171 μm2 cell size, containing >1.9 billion transistors.

关键词： Computer circuits

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A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array

A 32nm logic technology featuring 2nd-generation high-k + me...

引用

International Electron Devices Meeting (IEDM)

作者： S. Natarajan M. Armstrong M. Bost R. Brain M. Brazier C.-H. Chang V. Chikarmane M. Childs H. Deshpande K. Dev G. Ding T. Ghani O. Golonzka W. Han J. He R. Heussner R. James I. Jin C. Kenyon S. Klopcic S.-H. Lee M. Liu S. Lodha B. McFadden A. Murthy L. Neiberg J. Neirynck P. Packan S. Pae C. Parker C. Pelto L. Pipes J. Sebastian J. Seiple B. Sell S. Sivakumar B. Song K. Tone T. Troeger C. Weber M. Yang A. Yeoh K. Zhang Logic Technology Development Quality and Reliability Engineering TCAD Intel Corporation

A 32 nm generation logic technology is described incorporating 2 nd -generation high-k + metal-gate technology, 193 nm immersion lithography for critical patterning layers, and enhanced channel strain techniques. The transistors feature 9 Aring EOT high-k gate dielectric, dual band-edge workfunction metal gates, and 4 th -generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. Process yield, performance and reliability are demonstrated on a 291 Mbit SRAM test vehicle, with 0.171 mum 2 cell size, containing >1.9 billion transistors.

关键词： logic High K dielectric materials High-K gate dielectrics Lithography Capacitive sensors Silicon MOS devices Random access memory Testing Vehicles

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Low-K interconnect stack with thick metal 9 redistribution layer and Cu die bump for 45nm high volume manufacturing

Low-K interconnect stack with thick metal 9 redistribution l...

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2008 IEEE International Interconnect technology Conference, IITC

作者： Ingerly, D. Agraharam, S. Becher, D. Chikarmane, V. Fischer, K. Grover, R. Goodner, M. Haight, S. He, J. Ibrahim, T. Joshi, S. Kothari, H. Lee, K. Lin, Y. Litteken, C. Liu, H. Mays, E. Moon, P. Mule', T. Nolen, S. Patel, N. Pradhan, S. Robinson, J. Ramanarayanan, P. Sattiraju, S. Schroeder, T. Williams, S. Yashar, P. Logic Technology Development Intel Corporation Hillsboro OR 97229 United States Materials Intel Corporation Hillsboro OR 97229 United States Quality and Reliability Intel Corporation 5200 NE Elam Young Pkwy Hillsboro OR 97229 United States

ISBN: (纸本)9781424419111

Interconnect process features are described for a 45nm high performance logic technology. Through extensive use of highly manufacturable carbon doped oxide low-k dielectric layers and aggressive scaling of the SiCN etch stop film the Metal-1 to Metal-8 interconnect stack demonstrates a 10% average capacitance reduction over the 65nm process. The interconnect stack also features a very thick Metal-9 layer to provide a low resistance path for the power and I/O routing. The combined interconnect stack provides high performance and reliability and supports a Pb-free 45nm process. ©2008 IEEE.

关键词： Copper

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Multi-cell upset probabilities of 45nm high-k + metal gate SRAM devices in terrestrial and space environments

Multi-cell upset probabilities of 45nm high-k + metal gate S...

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46th Annual 2008 IEEE International reliability Physics Symposium, IRPS

作者： Seifert, N. Gill, B. Foley, K. Relangi, P. Logic Technology Development Q and R Intel Corporation Hillsboro OR 97124 United States Architecture for Quality and Reliability Intel Corporation Hillsboro OR 97124 United States Design and Technology Solutions Intel Corporation Hillsboro OR 97124 United States Stanford University Dept. of Electrical Engineering Stanford CA 94305 United States

ISBN: (纸本)9781424420506

Multi-cell soft errors are a key reliability concern for advanced memory devices. We have investigated single-bit (SBU) and multi-cell upset (MCU) rates of SRAM devices built in a 45nm high-k + metal gate (HK+MG) technology under neutron, proton and heavy-ion radiation. Our data highlight the excellent soft error reliability scaling properties of HK+MG. MCU rates were kept at 10% or less of SBU ones and bit-level SBU rates continue to decrease 2 per technology generation for terrestrial applications. SRAM upset rates in orbit are projected to be 2 to 4 orders of magnitude higher than at sea-level. A dramatic increase in MCU rates relative to SBU is projected for geosynchronous orbits, where direct ionization by heavy-ions dominates. No indication of charge amplification by parasitic bipolar devices has been observed for all investigated radiation environments. The observation that SBU error rates and small MCU error rates are elevated at locations in close proximity to well contacts for high LET values is speculated to be the result of the formation of a funnel between well contacts and sensitive drains. © 2008 IEEE.

关键词： Static random access storage

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