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IEEE International Conference on Interconnect technology

作者： D. Ingerly S. Agraharam D. Becher V. Chikarmane K. Fischer R. Grover M. Goodner S. Haight J. He T. Ibrahim S. Joshi H. Kothari K. Lee Y. Lin C. Litteken H. Liu E. Mays P. Moon T. Mule S. Nolen N. Patel S. Pradhan J. Robinson P. Ramanarayanan S. Sattiraju T. Schroeder S. Williams P. Yashar Logic Technology Development Intel Corporation Hillsboro OR USA Materials Intel Corporation Hillsboro OR USA Quality Reliability Intel Corporation Hillsboro OR USA

Interconnect process features are described for a 45nm high performance logic technology. Through extensive use of highly manufacturable carbon doped oxide low-k dielectric layers and aggressive scaling of the SiCN etch stop film the Metal-1 to Metal-8 interconnect stack demonstrates a 10% average capacitance reduction over the 65nm process. The interconnect stack also features a very thick Metal-9 layer to provide a low resistance path for the power and I/O routing. The combined interconnect stack provides high performance and reliability and supports a Pb-free 45nm process.

关键词： Resists Manufacturing processes Dielectric materials logic Inorganic materials Power distribution Robustness Polymers Moon Materials reliability

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Multi-cell upset probabilities of 45nm high-k + metal gate SRAM devices in terrestrial and space environments

Multi-cell upset probabilities of 45nm high-k + metal gate S...

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Annual International Symposium on reliability Physics

作者： N. Seifert B. Gill K. Foley P. Relangi Logic Technology Development Q&R Intel Corporation Hillsboro OR USA Architecture for Quality and Reliability Intel Corporation Hillsboro OR USA Design and Technology Solutions Intel Corporation Hillsboro OR USA Department of Electrical Engineering University of Stanford Stanford CA USA

Multi-cell soft errors are a key reliability concern for advanced memory devices. We have investigated single-bit (SBU) and multi-cell upset (MCU) rates of SRAM devices built in a 45 nm high-k + metal gate (HK+MG) technology under neutron, proton and heavy-ion radiation. Our data highlight the excellent soft error reliability scaling properties of HK+MG. MCU rates were kept at 10% or less of SBU ones and bit-level SBU rates continue to decrease 2times per technology generation for terrestrial applications. SRAM upset rates in orbit are projected to be 2 to 4 orders of magnitude higher than at sea-level. A dramatic increase in MCU rates relative to SBU is projected for geosynchronous orbits, where direct ionization by heavy-ions dominates. No indication of charge amplification by parasitic bipolar devices has been observed for all investigated radiation environments. The observation that SBU error rates and small MCU error rates are elevated at locations in close proximity to well contacts for high LET values is speculated to be the result of the formation of a funnel between well contacts and sensitive drains.

关键词： High K dielectric materials High-K gate dielectrics Random access memory Error analysis Protons Space technology Neutrons Ionization Error correction codes logic devices

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On the Scalability of Redundancy based SER Mitigation Schemes

On the Scalability of Redundancy based SER Mitigation Scheme...

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IEEE International Conference on Integrated Circuit Design and technology (ICICDT)

作者： N. Seifert B. Gill V. Zia M. Zhang V. Ambrose Logic Technology Development Q & R Intel Corporation Hillsboro OR USA Architecture for Quality and Reliability Intel Corporation Hillsboro OR USA Enterprise Microprocessor Group Intel Corporation Hillsboro OR USA Mobility Group Intel Corporation Folsom CA USA Enterprise Microprocessor Group Intgel Corporation Hudson MA USA

A novel circuit-level simulation strategy to assess the impact of charge sharing on the upset rate of redundancy based radiation hardened designs is introduced. Accelerated measurements conducted at the Los Alamos National Laboratory show a 10s or better reliability of hardened latches over standard latches for 45nm and 90nm implementations. Despite this encouraging trend, our simulations project that compact redundancy hardened designs will have soft error rates similar to non-hardened designs within a few technology generations if no additional mitigation techniques are applied to reduce the impact of charge sharing.

关键词： Scalability Redundancy Circuit simulation Error analysis Radiation hardening Space technology Computational modeling Clocks Latches Random access memory

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Fracture of Low‐k Dielectric Films and Interfaces

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AIP Conference Proceedings 2006年第1期817卷 83-91页

作者： T. Scherban G. Xu C. Merrill C. Litteken B. Sun Intel Corporation Logic Technology Development Quality & Reliability Hillsboro Oregon 97124 Intel Corporation California Technology Mfg. Corporate Quality Network Santa Clara California 95054

The mechanical properties of organosilicate glass films, also known as carbon‐doped oxide (CDO) films, were investigated and compared to dielectric constant, chemistry, interfacial properties and reliability performance. The techniques of four‐point bending and channel cracking were employed to measure the interfacial adhesion and cohesive strength of CDO films. The effect of compositional variations of the films on dielectric constant and elastic modulus was studied. It was found that changes in CDO film composition which decrease k also decrease the mechanical strength of the film. By contrast, a similar study of the effect of CDO film composition on interfacial adhesion showed that changes in film composition which decrease k have little effect on the adhesion energy of dielectric cap films to the low‐k film. The most significant factor controlling adhesion was found to be surface treatment conditions of the low‐k film. Studies of crack propagation in CDO films and interfaces as a function of humidity were carried out. It was shown that the phenomenon of stress‐corrosion cracking, whereby cracking is facilitated by the presence of moisture, is more pronounced for interfacial fracture than for CDO cohesive fracture. The effect of copper line orientation on fracture at the cap to Cu/low‐k interface was investigated using specially fabricated patterned test structures. It was found that the adhesion energy of the dielectric cap to patterned Cu/low‐k interface is lower for crack propagation parallel to the metal line direction than for propagation orthogonal to the metal line direction, consistent with stress relaxation results for identical test structures. Correlations between dielectric cap to Cu adhesion, stress relaxation and electromigration lifetime are shown.

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Adhesion Studies in Low‐k Interconnects Using Cross Sectional Nanoindentation

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AIP Conference Proceedings 2006年第1期817卷 104-109页

作者： J. M. Molina‐Aldareguia I. Ocaña D. Gonzalez M. R. Elizalde J. M. Sánchez J. M. Martínez‐Esnaola J. Gil Sevillano T. Scherban D. Pantuso B. Sun G. Xu B. Miner J. He J. Maiz CEIT and TECNUN (University of Navarra) P. Manuel Lardizabal 15 20018 San Sebastian Spain Intel Corporation Logic Technology Development Quality & Reliability Hillsboro Oregon 97124 Intel Corporation California Technology Mfg. Corporate Quality Network Santa Clara California 95054

The thermo‐mechanical robustness of interconnect structures is a key reliability concern for integrated circuits. Cross‐sectional nanoindentation (CSN) was developed to characterize the interfacial adhesion in blanket films deposited on silicon substrates. Recently, this technique has been adapted to the study of adhesion failure in real interconnect structures. The method has been applied to test chips simulating a portion of the interconnect structure and it has proven useful to study local adhesion effects in patterned structures. The test has been modelled using an FE code and cohesive elements developed in house to improve the understanding of the crack path and its interaction with the different structures present in the interconnect stack.

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Impact of interfacial chemistry on adhesion and electromigration in Cu interconnects

Impact of interfacial chemistry on adhesion and electromigra...

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Advanced Metallization Conference 2004, AMC 2004

作者： Zhou, Ying Scherban, Tracey Xu, Guanghai He, Jun Miner, Barbara Jan, Chia-Hong Ott, Andrew O'Loughlin, Jennifer Ingerly, Doug Leu, Jihperng Technology Development Quality and Reliability Logic Technology Development Intel Corporation Hillsboro OR 97124 Portland Technology Development Logic Technology Development Intel Corporation Hillsboro OR 97124

The impact of etch-stop (ES)/Cu interfacial chemistry on adhesion and electromigration (EM) has been systematically investigated by varying Cu surface chemistry, etch-stop film chemistry, metal capping layers, and thermal annealing conditions. Adhesion and EM improvement directly correlate with reducing interfacial oxygen for all the systems studied. While the adhesion of freshly deposited ES films strongly depends on the Cu surface chemistry and ES deposition conditions, the hermeticity of the ES film significantly impacts the film and interface chemistry during subsequent processing and thermal cycles, consequently affecting the long term stability of adhesion and electromigration performance. The mechanism for the correlation and material properties governing the interfacial chemistry will be discussed. © 2005 Materials Research Society.

关键词： Copper

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6-T cell circuit dependent GOX SBD model for accurate prediction of observed vccmin test voltage dependency

6-T cell circuit dependent GOX SBD model for accurate predic...

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Annual International Symposium on reliability Physics

作者： K. Mueller S. Gupta S. Pae M. Agostinelli P. Aminzadeh Design in Quality & Reliability Intel Design in Quality & Reliability Intel USA Logic Technology Development Q&R Intel USA

The effect of oxide soft breakdown (SBD) on the reliability of a 6-T cache cell has been examined and a circuit based gate oxide (GOX) reliability model has been developed. The results show that a model that combines the circuit topology, PMOS bias temperature (PMOS BT) effect, and a SBD time dependent leakage model allows for accurate prediction of the observed vccmin test voltage dependence. Through simulation it was determined that PMOS BT plays a significant role in aggravating SBD effects on stability. Examples are shown of cell stability using a simplified circuit SBD model including varying amounts of PMOS BT degradation on the two PMOS pull up devices, a SBD time evolution model for NMOS devices is explained, and finally a comprehensive model combining all of these effects is presented along with initial data verifying model trends.

关键词： Circuit testing Predictive models Voltage Circuit stability Electric breakdown Circuit topology Temperature dependence Circuit simulation Degradation MOS devices

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Interfacial adhesion of copper-low k interconnects

Interfacial adhesion of copper-low k interconnects

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IEEE International Conference on Interconnect technology

作者： E. Andideh T. Scherban B. Sun J. Blaine C. Block B. Jin Quality & Reliability Intel Corp. Hillsboro Oregon USA Quality & Reliability Intel Corp. Santa Clara California USA Logic Technology Development Intel Corp. Hillsboro Oregon USA Logic Technology Development Intel Corp. Hillsboro Oregon

ISBN: (纸本)0780366786

Adhesion energies of Cu-low k dielectric interfaces, measured with the technique of four-point bending, show a correlation to chemical mechanical polish results. A limit of 5 J/m/sup 2/ is established, below which thin film delamination and cracking are observed. In general, spin-on polymer dielectrics exhibit better adhesion to barrier films than carbon-doped oxide dielectrics. PVD barriers exhibit better adhesion to low k dielectric films than CVD barriers. Surface treatments of the dielectric film before barrier deposition are found to strongly modulate CVD barrier to spin-on polymer adhesion.

关键词： Adhesives Dielectric thin films Polymer films Dielectric films Dielectric measurements Energy measurement Mechanical variables measurement Chemical vapor deposition Delamination Atherosclerosis

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