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China Semiconductor technology International Conference (CSTIC)

作者： Wen Yan Fei Zhou Chengqing Wei Hai Zhao CanYang Xu Yong Li Jianhua Ju Weiguang Yang School of Materials Science and Engineering Shanghai University SMIC Logic Technology and Development Center

The FinFET device shows well Gate control ability on the channel charge beyond the 14nm and sub-14nm node due to superior electrostatic control ability. The Sub Fin Bottom punch through is a major concern for the 14nm and sub-14nm FinFET device. The high dose punch through stop IMP is popularly used to control the Fin Bottom punch through, but it suffered Fin damage and device performance degradation. Thus, in this paper, a new channel stop method of Solid Source Doping (SSD) was investigated because of its better doping profile control, lower Fin damage. In this paper we reported the SSD SIMS data both on the blanket wafer and the structure wafer, and the Dopant profile result comparison between the IMP and the SSD method based on the TCAD, verified the reliability and advantage of SSD.

关键词： FinFETs Films Doping profiles Performance evaluation Solids logic gates

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Challenges and characterization of 14nm N-type bulk FinFET

Challenges and characterization of 14nm N-type bulk FinFET

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China Semiconductor technology International Conference (CSTIC)

作者： Yong Li Jianhua Ju Miao Liao Logic Technology and Development Center SMIC

ISBN: (纸本)9781479972425

FinFET device has better electrostatic performance than planar device and makes devices further scaling possible. N-type bulk FinFET process challenges such as implantation induced Fin damages, Source/Darin (S/D) epitaxy and Fin profile control were discussed. Pre-Fin anti-punch trough (APT) implantation and low beam current n-type light-doped-drain (NLDD) implantation combined with optimized post-implant annealing are both benefit to eliminate or reduce the implantation induced Fin damages. Within S/D Si epitaxy process, contact resistance, resistor resistance and transistor external resistance were much reduced. With the optimized process, n-type bulk FinFET device performance was much improved. Gate oxide performance and electron mobility were compared with previous generations; swing slope and drain induced barrier lowering were also got from the IdVg curves. Some reliability evaluations such as GOI, TDDB and HCI were performed and passed the specifications. For n-type bulk FinFET further improvement directions were proposed at last.

关键词： logic gates Silicon Epitaxial growth Human computer interaction Process control MOS devices Random access memory

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Study of fin CD controllability for FinFET manufacturing

Study of fin CD controllability for FinFET manufacturing

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China Semiconductor technology International Conference (CSTIC)

作者： Hai Zhao Gang Mao Rex Yang Technology Research and Development SMIC Logic Technology and Development Center SMIC Shanghai China

In this paper, several steps which would affect CD variation or Fin CD loss were analyzed during FinFET manufacturing, and then we figured out the dominant ones causing CD loss. Finally, an optimization guideline for Fin CD control in process integration was suggested for better Fin CD controllability. It's not only good for Fin CD control, but also good for wide process margin to integrate smaller Fin CD beyond 20nm technology node.

关键词： logic gates Performance evaluation FinFETs Industries Mass production Surface treatment Annealing

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Optimization of STI oxide recess uniformity for FinFET beyond 20nm

Optimization of STI oxide recess uniformity for FinFET beyon...

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China Semiconductor technology International Conference (CSTIC)

作者： Lijuan Du Hai Zhao Weiguang Yang Rex Yang Larry Chen Shaofeng Yu Gang Mao Qingling Wang Yangkui Lin Shicheng Ding Zhengling Chen School of Materials Science and Engineering Shanghai University Technology Research and Development SMIC Logic Technology and Development Center SMIC Shanghai China

In the process of the FinFETs, shallow trench isolation (STI) oxide recess is very critical to fin height control which has significant impact on the electrical performance of device. In this work, void free STI gap filling process has been demonstrated with process optimization. STI CMP uniformity for both global and local areas has been studied. STI oxide shape and recess uniformity have also been evaluated with different oxide recess methods. Good STI oxide profile and uniformity of STI oxide recess have been achieved through above process optimization.

关键词： Etching Optimization FinFETs Performance evaluation Filling

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Techniques to improve read noise margin and write margin for bit-cell of 14nm FINFET node

Techniques to improve read noise margin and write margin for...

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China Semiconductor technology International Conference (CSTIC)

作者： Gong Zhang Yu Li Shaofeng Yu Logic Technology and Development Center SMIC Pudong New Area Shanghai P.R. China

The implementation of FINFET devices in the SRAM cell provides many benefits over that of planar bulk devices. The short channel effect, drive current and mismatch can be better controlled. Several FIN number options among PU(pull up device), PD(pull down device) and PG(pass gate device) can be selected to achieve the good read noise margin and write margin. But in highest-density SRAM cell, in order to minimize the bit-cell area, 3 devices are designed as one FIN only for each. The write margin is suffered deeply by this option unfortunately Some techniques are presented in this paper to increase the yield window of FINFET SRAM with limited FIN number. Some of them are based on process or device performance optimization, such as PG Vt implant, FIN thickness, channel orientation modification, DG device and asymmetrical device, others are based on circuit design, including bit-cell and periphery circuit, such as read or write assist circuit, 8T or 10T cell. With these actions, the better yield window can be achieved. The side effects of these actions are evaluated also, such as the area penalty, complex process and the cost more.

关键词： logic gates FinFETs Doping Noise Layout Silicon

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Dummy poly removal impact factors and improvement in HKMG last process

Dummy poly removal impact factors and improvement in HKMG la...

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作者： Zeng, Yizhi Zhao, Jie Gao, Hanjie Awuti, Kurban Song, Woeiji Yu, Shaofeng Zhang, Qin Lin, Yihui Liu, Jialei Liu, H.X. Logic Technology and Development Center SMIC 201312 China

ISBN: (纸本)9781607685395

For 20/16nm HK-last and MG-last process, Dummy poly is removed by Wet process. This paper studies the factors impacting the dummy poly removal process, and presents some models to explain the impacting factors. Implant process is one of main factors influencing dummy poly removal capability because the differences of implant ions and doping amount into dummy poly induce difference of poly removal rate by wet process. We also study poly surface single clean, multiple clean and thermal process. Based on the model, we plan N-type doping poly and P-type doping poly with different ion doping amounts on blank wafer and 20nm structure wafers to evaluate dummy poly removal. We find dummy poly removal rate is different between N-type doping poly and P-type doping poly, and receive different dummy poly removal trend by ion amount on N-type doping poly and P-type doping poly. The model can help to improve dummy poly removal process control. © 2014 The Electrochemical Society.

关键词： Ions

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Interfacial layer development for 20nm high-k last integration scheme

Interfacial layer development for 20nm high-k last integrati...

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作者： Gao, Hanjie Zhao, Jie Min, Jiahua Zeng, Yizhi Awut, Kurban Song, Woeiji Yu, Shaofeng School of Materials Science and Engineering Shanghai University China Logic Technology and Development Center SMIC China

ISBN: (纸本)9781607685395

With the characteristic dimension scaling down of CMOS device, the gate leakage increases significantly and the device gets low reliability performance. Then EOT (Equivalent Oxide Thickness) should be decreased, and more performance would be gained with leakage and reliability sacrifice by an optimized dielectric interfacial layer and high-k material. In this paper, the methods to form IL are the key point of EOT scaling down with gate leakage sacrifice and post replacement metal gate (RMG) treatment lead to work function improvement with hysteresis reduction beyond 20nm node of CMOS devices. Based on data analysis we want to get some optimized conditions to make this layer an enhancement in the research of HKMG logic product process development. © 2014 The Electrochemical Society.

关键词： CMOS integrated circuits

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Stacking faults and stress memorization technique study for n-type MOSFET performance improvement in all last High-k Metal Gate process development

Stacking faults and stress memorization technique study for ...

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作者： Li, Yong Sun, Hao Ju, Jianhua Logic Technology and Development Center SMIC 201203 China School of Materials Science and Eng Shanghai University 200072 China

ISBN: (纸本)9781607685395

In this paper, the stacking faults, stress memorization technique (SMT) and their impacts on n-type MOSFET device performance were studied. SMT combines source/drain deep PAI improves short channel device electron mobility 25%, Ion/Ioff curve 8% and long channel device 10% and 4%, respectively. A mechanism why SMT improves device performance in all last HKMG (High-k Metal Gate) process was proposed. During SMT anneal, poly expands much more than the hard nitride cap, the thermal stress gain from poly transformation from an elastic state to a plastic state was transferred into the channel, the stress was then memorized by the source/drain stacking faults, that were formed during the SMT anneal at deep pre-amorphous source/drain area. After poly removal, the tensile stress still exists, as it was retained by the stacking faults. The stress intensity along channel, Sxx, is the key parameter to index the stress effect on device performance improvement;it is related to poly volume and gate length. And based on this, the reasons that long channel and short channel devices performance gain are much smaller than that of the middle channel devices were also discussed. © 2014 The Electrochemical Society.

关键词： Stacking faults

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Arsenic dimer (As2+) Lightly Doped Drain(LDD)implantation study for 20nm logic device development

Arsenic dimer (As2+) Lightly Doped Drain(LDD)implantation st...

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作者： Sun, Hao Li, Yong Zhang, Shuai Xie, Xinyun Cai, Gorge Zhou, Zuyuan Shi, Xuejie He, Yonggen Shi, Weimin Ju, Jianhua Chen, Larry Yu, Shaofeng School of Materials Science and Eng Shanghai University 200072 China Logic Technology and Development Center SMIC 201203 China

ISBN: (纸本)9781607685395

Process variation presents a significant challenge to future scaling of VLSI technology. Junction depth scaling with small Vth variation is required for the 45 nm technology node and beyond. Variations in MOSFET characteristics due to random dopant fluctuation (RDF) may become a fundamental limit to device scaling and circuit complexity. Arsenic dimer (As2+) implant has been used for the formation of ultra-shallow source drain extensions for NMOS transistors below 45nm, CMOS logic process. As Dimer requires only half the dose and twice the energy of equivalent As+ so it is more favorable for much lower energy (+ implantation. However, arsenic dimer implantation showed better Vth mismatch performance than conventional As+ implantation. © 2014 The Electrochemical Society.

关键词： Capacitance

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NMOS Narrow Width Devices Drive Current Improvements through STI Processes and Channel Implantation Optimization

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ECS Transactions 2010年第1期27卷

作者： Zhaoxu Shen Jianhua Ju Brisk Wang Allan Zhou Jinhua Liu H.-M. Ho X.-J. Ning Logic Technology Development Center Semiconductor Manufacturing International Corporation Wenchang Road #18 Beijing Beijing 100176 China Logic Technology Development Center Semiconductor Manufacturing International Corporation Semiconductor Manufacturing International Corporation Wenchang Road #18 Beijing Beijing 100176 China LTD Logic2 Device SMIC(BJ) BeiJing BeiJing 100176 China Semiconductor Manufacturing International Corporation

NMOS narrow width transistor driving current as a function of shallow trench isolation (STI) processes and channel implant conditions were studied on a 65nm CMOS technology. It is found that the magnitude of compressive stress in STI could modulate the trend of NMOS drive current versus width dependence that was attributed to channel dose profile uneven distribution under the influence of stress. It is seen that the channel body effect factor (gamma) of large width (W=10um) transistor is smaller than that of narrow width device (W=0.12um). This difference increases as STI compressive stress scales up. The phenomena are consistent with the analysis that Boron dose distribution varies as STI stress changes. it is shown that the down trend of drive current for narrow width transistors could be minimized by STI process optimization, or by introducing indium implantation during channel implantation processes.

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