This book offers readers broad coverage of techniques to model, verify and validate the behavior and performance of complex distributed embeddedsystems. The authors attempt to bridge the gap between the three d...
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ISBN:
(数字)9781461438793
ISBN:
(纸本)9781461438786;9781493901203
This book offers readers broad coverage of techniques to model, verify and validate the behavior and performance of complex distributed embeddedsystems. The authors attempt to bridge the gap between the three disciplines of model-based design, real-time analysis and model-driven development, for a better understanding of the ways in which new development flows can be constructed, going from system-level modeling to the correct and predictable generation of a distributed implementation, leveraging current and future research results.
Full-System (FS) simulation is essential for performance evaluation of complete systems that execute complex applications on a complete software stack consisting of an operating system and user applications. Neverthel...
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Full-System (FS) simulation is essential for performance evaluation of complete systems that execute complex applications on a complete software stack consisting of an operating system and user applications. Nevertheless, they require careful fine-tuning against real hardware to obtain reliable performance statistics, which can become tedious, error-prone, and time-consuming with typical trial-and-error approaches. We propose a novel, streamlined, component-level calibration methodology to address these shortcomings to validate FS simulation models. Our methodology greatly accelerates the validation process without sacrificing accuracy. It is Instruction Set Architecture (ISA)-agnostic, and can tackle hardware specifications at different levels of detail. We demonstrate its effectiveness by validating FS models against both open-hardware and IP-protected (closed hardware) RISC-V silicon, achieving a mean error of 19-23% for the SPEC CPU2017 suite in the two cases. We introduce the first open-source RISC-V-based FS-validated simulation models with a complete and replicable methodology.
Modern processors experience memory contention when the speed of their computational units exceeds the rate at which new data is available to be processed. This phenomenon is well known as the memory wall and is a gre...
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Modern processors experience memory contention when the speed of their computational units exceeds the rate at which new data is available to be processed. This phenomenon is well known as the memory wall and is a great challenge in computer engineering. The reason for this phenomenon is the unequal growth rate in memory access speeds compared to processor clock rates. In order to mitigate the memory bottleneck in classic computer architectures, a scalable parallel computing platform called the Grid of Processing Cells (GPC) has been proposed. To evaluate its effectiveness, the GPC is modeled at the instruction-level and functional-level using SystemC TLM-2.0, with a focus on memory contention. Individual GPC cells can be switched between the two abstraction levels. Our mixed-level system model enables fast and accurate simulations. We test multiple streaming applications on the GPC, analyze software-based optimization methods and their effects on the GPC, at both abstraction levels. The performance is then compared against the traditional shared memory processor (SMP) architecture. Experimental results show improved execution times on the GPC primarily due to a large decrease in main memory contention.
作者：
JACKSON, L.L.GRANT, J.C.USNCaptain L. L. Jackson
Jr. USN is the first Commanding Officer of the Atlantic Undersea Test and Evaluation Center (AUTEC). This center is a field activity of the Naval Ship Systems Command with the headquarters located in Orlando Florida. The ranges for testing and evaluating advanced underseas systems are located in the Tongue of The Ocean Bahamas Islands. He began his career in 1942 with an appointment from the State of Alabama to the United States Naval Academy. He was graduated in 1945 and after a brief indoctrination in aviation at Jacksonville Fla. began a career in submarines. He has served in submarines both in Atlantic and Pacific fleets. His regular or temporary assignments have included duty on four fleet type submarines six Polaris submarines and four nuclear powered attack submarines. After a tour on the staff of a Submarine Squadron Commander as Squadron Engineer he applied for and was selected for Engineering Duty in 1959. As an Engineer Duty Officer he has served at Pearl Harbor Naval Shipyard David Taylor Model Basin the Design Division of the Bureau of Ships and on the staff of the Chief of Naval Materiel. He began his present tour of duty on 1 July 1966. Captain Jackson holds a Master of Science degree in Naval Engineering (Electrical) from the United States Naval Postgraduate School
Monterey California is a member of the United States Naval Institute
the Marine Technology Society and the American Society of Naval Engineers. He has published two papers in the Journal of Naval Engineers. In 1962 he was awarded the Secretary of the Navy Award for Special Achievement for work done at David Taylor Model Basin. Mr. John C. Grant was born in Detroit
Michigan and holds a B.S. degree in Electrical Engineering from the U.S. Naval Academy 1956. He is married to the former Olga (Mickey) Markham and they have five children. Mr. Grant has the distinction of being one of the founders of the American Acoustical Society Marine Technology Society. He served with the U. S. Navy from June
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