This paper focuses on bridging the gap between theory and practice in the management of host CPU and link resources for real-time communication. Using our implementation of real-time channels, a paradigm for real-time...
详细信息
This paper focuses on bridging the gap between theory and practice in the management of host CPU and link resources for real-time communication. Using our implementation of real-time channels, a paradigm for real-time communication in packet-switched networks, we illustrate the tradeoff between resource capacity and channel admissibility, which determines the number and type of real-time channels that can be accepted for service and the performance delivered to best-effort traffic. We demonstrate that this tradeoff is affected significantly by the choice of implementation paradigms and the grain at which CPU and link resources are multiplexed amongst active channels. To account for this effect we extend the admission control procedure for real-time channels originally proposed using idealized resource models. Our results show that practical considerations significantly reduce channel admissibility compared to idealized resource models. Further, the optimum choice of multiplexing grain depends on several factors such as resource preemption overheads, the relationship between CPU and link bandwidth, and the interaction between link bandwidth allocation and CPU bandwidth allocation.
Parallel machines have the potential to satisfy the large computational demands of emerging real-time applications. These applications require a predictable communication network, where time-constrained traffic requir...
详细信息
Parallel machines have the potential to satisfy the large computational demands of emerging real-time applications. These applications require a predictable communication network, where time-constrained traffic requires bounds on latency or throughput while good average performance suffices for best-effort packets. This paper presents a router architecture that tailors low-level routing, switching, arbitration and flow-control policies to the conflicting demands of each traffic class. The router implements deadline-based scheduling, with packet switching and table-driven multicast routing, to bound end-to-end delay for time-constrained traffic, while allowing best-effort traffic to capitalize on the low-latency routing and switching schemes common in modern parallel machines. To limit the cost of servicing time-constrained traffic, the router shares packet buffers and link-scheduling logic between the multiple output ports. Verilog simulations demonstrate that the design meets the performance goals of both traffic classes in a single-chip solution.
We consider the message transmission problem in unidirectional slotted ring networks. We consider two operation modes: 1) the evacuation mode, in which all messages arrive before system initialization and no new messa...
详细信息
We consider the message transmission problem in unidirectional slotted ring networks. We consider two operation modes: 1) the evacuation mode, in which all messages arrive before system initialization and no new message arrives during system operation; and 2) the continuation mode, in which new messages may arrive after system initialization. We study the performance of several message scheduling policies with respect to three performance measures: meeting all message deadlines, minimizing the maximum delay or the total length of busy periods, and minimizing the average delay. We show that the least-slack-time-first (LSF) scheduling policy is optimal in evacuation mode operation with respect to meeting all message deadlines, while no optimal scheduling policy can possibly exist for continuation mode operation. For the other two performance measures, we show that in the case when messages may be of variable lengths: 1) the farthest-destination-first (FDF) policy is optimal in terms of minimizing the maximum delay and minimizing the total length of busy periods for evacuation mode and for continuation mode operation, respectively, and 2) no optimal scheduling policy can possibly exist in terms of minimizing the average delay under either evacuation mode or continuation mode operation.
In this paper we present some novel algorithms for scheduling hierarchical signal flow graphs in the domain of high-level synthesis. There are several key contributions of this paper. First, we develop a novel extensi...
详细信息
In this paper we present some novel algorithms for scheduling hierarchical signal flow graphs in the domain of high-level synthesis. There are several key contributions of this paper. First, we develop a novel extension of the force directed scheduling problem which naturally handles loops and conditionals by coming up with a scheme of scheduling hierarchical signal flow graphs. Second, we develop three new parallel algorithms for the scheduling problem. Third, our parallel algorithms are portable across a wide range of parallel platforms. We report results on a set of high-level synthesis benchmarks on 8-processor SGI Challenge and a network of 4 SUN SPARCstation5 work stations. Finally, while some parallel algorithms for VLSI CAD reported by earlier researchers have reported a loss of qualities of results, our parallel algorithms produce exactly the same results as the sequential algorithms on which they are based.
Scientific applications often require some strategy for temporary data storage to do the largest possible simulations. The use of virtual memory for temporary data storage has received criticism because of performance...
详细信息
ISBN:
(纸本)9780897918541
Scientific applications often require some strategy for temporary data storage to do the largest possible simulations. The use of virtual memory for temporary data storage has received criticism because of performance problems. However, modern virtual memory found in recent operating systems such as Cenju-3/DE give application writers control over virtual memory policies. We demonstrate that custom virtual memory policies can dramatically reduce virtual memory overhead and allow applications to run out-of-core efficiently. We also demonstrate that the main advantage of virtual memory, namely programming simplicity, is not lost.
Scientific applications often require some strategy for temporary data storage to do the largest possible simulations. The use of virtual memory for temporary data storage has received criticism because of performance...
详细信息
Scientific applications often require some strategy for temporary data storage to do the largest possible simulations. The use of virtual memory for temporary data storage has received criticism because of performance problems. However, modern virtual memory found in recent operating systems such as Cenju-3/DE give application writers control over virtual memory policies. We demonstrate that custom virtual memory policies can dramatically reduce virtual memory overhead and allow applications to run out-of-core efficiently. We also demonstrate that the main advantage of virtual memory, namely programming simplicity, is not lost.
This paper describes a method based on self-feedback for controlling both chaotic and nonchaotic forms of the Hénon map with and without additive Gaussian white noise. We describe a nonlinear self-tuning controll...
This paper describes a method based on self-feedback for controlling both chaotic and nonchaotic forms of the Hénon map with and without additive Gaussian white noise. We describe a nonlinear self-tuning controller that makes use of a feedback reference signal and a linear autoregressive formulation for the gain. This controller is effective at stabilizing the map to a variety of fixed point or period-two orbits. We contrast our approach with the method of Ott, Grebogi, and Yorke [Phys. Rev. Lett. 64, 1196 (1990)] which has been used to control some chaotic processes and recently, some nonchaotic, stochastic ones.
Human brain function is studied by averaging many PET images in order to enhance the signal to noise ratio of weak group-specific patterns caused by medication, illness, or functional activation. Present registration ...
详细信息
Human brain function is studied by averaging many PET images in order to enhance the signal to noise ratio of weak group-specific patterns caused by medication, illness, or functional activation. Present registration methods by Woods and Friston (SPM), compute 3 translations and 3 rotations to register each PET image to a reference anatomical atlas using a 6 degree of freedom optimization method. By using only a 2 degree of freedom optimization method, the present method decreases the computing time down to 70 sec in a SUN Sparc2 CPU; this is a speed increment by a factor of 3 to 15 times over previous methods. Experimental results for 24 FDG-PET images also indicate that the present method improves the accuracy of the registration to a mean error of 0.48 mm and a maximum error of 2.47 mm.
We study time-resolved-spectra of InGaN and GaN diodes with a short electrical pulse. LEDs with four different structures were studied: the bulk InGaN/GaN blue LED (/spl lambda//sub peak/ = 450 nm); the InGaN single q...
详细信息
We study time-resolved-spectra of InGaN and GaN diodes with a short electrical pulse. LEDs with four different structures were studied: the bulk InGaN/GaN blue LED (/spl lambda//sub peak/ = 450 nm); the InGaN single quantum well (SQW) blue LED (/spl lambda//sub peak/ = 470 nm); the InGaN SQW green LED (/spl lambda//sub peak/ = 525 nm); and the Zn disordered GaN active layer (/spl lambda//sub peak/ = 430 nm). When pumped with short electrical pulses, some of them can generate UV light. The electrical pump time-resolved spectrum studies provide a convenient tool to investigate the recombination process in the GaN material system. The results show that the UV emissions from bulk GaN and bulk InGaN materials, and the blue as well as the green emissions from the high efficiency InGaN SQW LEDs, correspond to bandedge transitions.
Opens in BICMOS structures are analyzed here. It is shown that some opens cannot be detected by stuck-fault or other functional tests, since some transistors in BiCMOS gates do not affect the logical function of the g...
详细信息
Opens in BICMOS structures are analyzed here. It is shown that some opens cannot be detected by stuck-fault or other functional tests, since some transistors in BiCMOS gates do not affect the logical function of the gate. A switch-level model for CMOS circuits is extended to include bipolar devices. With this switch-level model, opens that cannot be detected by stuck-faults or other functional tests are easily identified. It is also shown that, in BICMOS circuits, an open defect in one transistor can accelerate the wearout of another nondefective transistor.
暂无评论