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2024 IEEE Symposium on VLSI technology and Circuits, VLSI technology and Circuits 2024

作者： Fukushima, T. Kashima, T. Seto, S. Ohtori, H. Kato, M. Katou, K. Takehira, H. Sugawara, Y. Zhu, Z. Hara, K. Osanai, R. Beppu, T. Tahara, H. Ishiku, T. Takahashi, K. Ariga, T. Ueda, Y. Matamura, Y. Mukae, Y. Takeguchi, N. Maruyama, Y. Nishikawa, R. Kitagawa, H. Asakawa, J. Uchiyama, Y. Ohuchi, K. Sekine, K. Advanced Memory Development Center Japan Western Digital Corporation 800 Yamanoissiki-Cho Mie-Pref Yokkaichi512-8550 Japan Institute of Memory Technology Research & Development Kioxia Corporation Japan

ISBN: (纸本)9798350361469

A state-of-the-art fluorine-free word line (WL) molybdenum (Mo) process has been established for future 3D flash memory. Application of Mo to WLs can accelerate scaling of cells in both the vertical and horizontal directions with lower RC delay and lower leakage failure rates compared to traditional tungsten. In addition to being fluorine-free, key attributes of the process are optimization of Mo recess by innovative chemical and improvement of Mo filling to remove oxygen residue in Mo voids. These techniques can extend the scaling limit of 3D flash memory. © 2024 IEEE.

关键词： Fluorine free molybdenum oxygen scalability word line

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Highly Scalable Metal Induced Lateral Crystallization (MILC) Techniques for Vertical Si Channel in Ultra-High (> 300 Layers) 3D Flash memory

Highly Scalable Metal Induced Lateral Crystallization (MILC)...

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2023 IEEE Symposium on VLSI technology and Circuits, VLSI technology and Circuits 2023

作者： Ishihara, N. Shimada, Y. Ochi, T. Seto, S. Matsuo, H. Yamashita, H. Morita, S. Ukishima, M. Uejima, K. Arayashiki, Y. Kajiwara, S. Murayama, A. Nishiyama, K. Sugimae, K. Mori, S. Saito, Y. Shundo, T. Maeda, A. Kamiya, H. Uchiyama, Y. Fujiwara, M. Aiso, F. Sekine, K. Ohtani, N. Advanced Memory Development Center Japan Institute of Memory Technology Research & Development Kioxia Corporation Japan Western Digital Corporation 800 Yamanoissiki-Cho Mie-Pref Yokkaichi512-8550 Japan

ISBN: (纸本)9784863488069

State-of-the-art Metal Induced Lateral Crystallization (MILC) techniques have been demonstrated for 3D flash memory with ultra-high (over 300) layers. For the first time, 14-μm-long macaroni silicon (Si) channels in vertical memory hole are fully single-crystallized. Furthermore, by using newly developed nickel (Ni) gettering technique, the 112 word-line-layer 3D flash memory exhibits cell array performances such as read noise reduction of 40% or more, and 10-times channel conductance without any degradations of cell reliability. © 2023 JSAP.

关键词： Flash memory

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In silico screening for As/Se-free ovonic threshold switching materials

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npj Computational Materials 2023年第1期9卷 1359-1366页

作者： Sergiu Clima Daisuke Matsubayashi Taras Ravsher Daniele Garbin Romain Delhougne Gouri Sankar Kar Geoffrey Pourtois imec Kapeldreef 75B-3001 LeuvenBelgium Device Technology Research&Development Center Future Memory Development DepartmentKIOXIA CorporationShin-sugita-cho 8Isogo-kuYokohamaJapan KU Leuven Celestijnenlaan 200DB-3001 LeuvenBelgium

Restricted use of hazardous environmental chemicals is one important challenge that the semiconductor industry needs to face to improve its *** threshold switching(OTS)ternary compound materials used in memory selector devices contain As and *** these elements out of these materials requires significant research *** facilitate this process,we performed systematic material screening for As/Se-free ternary materials,based on ab-initio *** limit the large amount of possible chemical compositions to fewer promising candidates,we used physics-based material parameter filters like material stability,electronic properties,or change in *** OTS gauge concept is introduced as a computed parameter to estimate the probability of a material to show an OTS *** a result,we identified 35 As/Se-free ternary alloy compositions for stand-alone OTS memory applications,as well as 12 compositions for RRAM selector *** work aims seeding the development of As/Se-free OTS materials.

关键词： alloy ternary free

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Fabrication of Dual Damascene structure with Nanoimprint lithography and Dry-etching

Fabrication of Dual Damascene structure with Nanoimprint lit...

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Novel Patterning Technologies 2023

作者： Takeuchi, Norikazu Hasegawa, Genna Komukai, Toshiaki Iwasaki, Takahiro Hatano, Masayuki Komori, Motofumi Kono, Takuya Process Technology Research & Development Center Institute of Memory Technology Research & Development Kioxia Corporation 800 Yamanoissiki-cho Yokkaichi-shi Mie-ken512-8500 Japan

ISBN: (纸本)9781510661011

Nanoimprint lithography (NIL) has received attention as alternative lithographic technology, which can fabricate fine patterns of semiconductor devices at low cost. Application of NIL may lead to the reduction of number of process steps and cost of manufacturing of dual-damascene structure, by simultaneous fabrication of holes and trenches. Therefore, in this study, we investigated fabrication of dual-damascene structure using NIL and dry-etching. However, the difficulty in dry-etching process is high as the holes and trenches are etched together using single resist mask. Suppression of defects during the NIL process and the suppression of resist consumption and CD shift during the etching process, is critical. To address these issues, we used a high etching resistance resist, optimized the NIL process to reduce defects, and optimized the template structure and etching process to suppress resist consumption and CD shift. As a result, a dual-damascene structure with L/S = 4X/4X nm was obtained. © 2023 SPIE.

关键词： Nanoimprint lithography

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Optimal Design of WET Etching Bath for 3D Flash Memories Using Multi-Objective Bayesian Optimization 30

Optimal Design of WET Etching Bath for 3D Flash Memories Usi...

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30th International Symposium on Semiconductor Manufacturing, ISSM 2024

作者： Kouda, Miyuki Mori, Yumi Sugita, Tomohiko Ng, Youyang Kioxia Corporation Ai and System Research Center Frontier Technology R and D Institute Yokkaichi-shi Japan Kioxia Corporation Ai and System Research Center Frontier Technology R and D Institute Yokohama-shi Japan Kioxia Corporation Advanced Memory Process Development Center Memory Division Yokkaichi-shi Japan

ISBN: (纸本)9798331510589

In recent years, the complexity of semiconductor manufacturing processes has increased, leading to a growing need for the high-precision optimization of device structures. For example, in batch-type wet etching devices, the flow of chemical liquids within the process bath can vary depending on the device structure, causing variations in the etching state of the wafer. This issue is addressed using a feedback mechanism that iteratively adjusts the device structure based on the results of an etching experiment, thereby achieving more uniform etching conditions. However, this approach requires a large number of trial experiments. In the fabrication process of 3D flash memories, word-line formation in the silicon substrate requires precise control of the silicon concentration in the etching solution. However, this concentration can fluctuate due to the dissolution of the SiN film during the etching process. This fluctuation may cause various problems. This study introduces an innovative method utilizing multi-objective Bayesian optimization to derive optimal wet etching bath design parameters;this method is informed by image and physical-quantity data from fluid dynamics simulations [1]. This approach is validated through simulation experiments, whose results are used to identify the best possible wet etching bath designs effectively. © 2024 IEEE.

关键词： Wet etching

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Fluorine-free Word Line Molybdenum Process for Enhancing Scalability and Reliability in 3D Flash memory

Fluorine-free Word Line Molybdenum Process for Enhancing Sca...

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Symposium on VLSI technology

作者： T. Fukushima T. Kashima S. Seto H. Ohtori M. Kato K. Katou H. Takehira Y. Sugawara Z. Zhu K. Hara R. Osanai T. Beppu H. Tahara T. Ishiku K. Takahashi T. Ariga Y. Ueda Y. Matamura Y. Mukae N. Takeguchi Y. Maruyama R. Nishikawa H. Kitagawa J. Asakawa Y. Uchiyama K. Ohuchi K. Sekine Advanced Memory Development Center Western Digital Corporation Yokkaichi Japan Institute of Memory Technology Research & Development Kioxia Corporation

ISBN: (数字)9798350361469

ISBN: (纸本)9798350361476

关键词： Three-dimensional displays Scalability Tungsten Very large scale integration Filling Dielectrics Reliability

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Correcting on-chip distortion of control pulses with silicon spin qubits

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Chinese Physics B 2025年第1期34卷 265-271页

作者： Ming Ni Rong-Long Ma Zhen-Zhen Kong Ning Chu Wei-Zhu Liao Sheng-Kai Zhu Chu Wang Gang Luo Di Liu Gang Cao Gui-Lei Wang Hai-Ou Li Guo-Ping Guo CAS Key Laboratory of Quantum Information University of Science and Technology of China(USTC)Hefei 230026China CAS Center for Excellence in Quantum Information and Quantum Physics University of Science and Technology of ChinaHefei 230026China Integrated Circuit Advanced Process Research and Development Center Institute of MicroelectronicsChinese Academy of Sciences(CAS)Beijing 100029China Hefei National Laboratory Hefei 230088China Beijing Superstring Academy of Memory Technology Beijing 100176China Origin Quantum Computing Company Limited Hefei 230026China

In semiconductor quantum dot systems,pulse distortion is a significant source of coherent errors,which impedes qubit characterization and ***,we demonstrate two calibration methods using a two-qubit system as the detector to correct distortion and calibrate the transfer function of the control *** methods are straightforward to implement,robust against noise,and applicable to a wide range of qubit *** two methods differ in correction accuracy and *** first,coarse predistortion(CPD)method,partially mitigates *** second,all predistortion(APD)method,measures the transfer function and significantly enhances exchange oscillation *** methods use exchange oscillation homogeneity as the metric and are suitable for any qubit driven by a diabatic *** believe these methods will enhance qubit characterization accuracy and operation quality in future applications.

关键词： quantum computation quantum dot pulse distortion

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Lack of interferon regulatory factor 3 leads to anxiety/depression-like behaviors through disrupting the balance of neuronal excitation and inhibition in mice

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Genes & Diseases 2023年第3期10卷 1062-1074页

作者： Junjie Li Yayan Pang Yehong Du Lei Xia Mulan Chen Yepeng Fan Zhifang Dong Pediatric Research Institute Ministry of Education Key Laboratory of Child Development and DisordersNational Clinical Research Center for Child Health and DisordersChina International Science and Technology Cooperation Base of Child Development and Critical DisordersChongqing Key Laboratory of Translational Medical Research in Cognitive Development and Learning and Memory DisordersChildren's Hospital of Chongqing Medical UniversityChongqing 400014China

Disrupting the balance of neuronal excitation and inhibition (E/I) is an important pathogenic mechanism of anxiety and depression. Interferon regulatory factor 3 (IRF3) plays a key role in the innate immune response, and activation of IRF3 triggers the expression of type I interferons and downstream interferon-stimulated genes, which are associated with anxiety and depression. However, whether IRF3 participates in the pathogenesis of anxiety/depression by regulating E/I balance remains poorly understood. Here, we reported that global knockout (KO) of IRF3 (IRF3^(−/−)) significantly increased anxiety/depression-like behaviors, but did not affect normal spatial learning and memory. Compared with wild type (WT) control mice, the E/I balance was disrupted, as reflected by enhanced glutamatergic transmission and decreased GABAergic transmission in the neurons of hippocampal CA1 and medial prefrontal cortex (mPFC) in IRF3-KO mice. Importantly, genetic rescue of IRF3 expression by adeno-associated virus (AAV) was sufficient to alleviate anxiety/depression-like behaviors and restore the neuronal E/I balance in IRF3-KO mice. Taken together, our results indicate that IRF3 is critical in maintaining neuronal E/I balance, thereby playing an essential role in ensuring emotional stability.

关键词： Anxiety Depression Hippocampus IRF3 Medial prefr ontal cortex Synaptic transmission

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Space-filling experimental design for efficient Bayesian optimization 30

Space-filling experimental design for efficient Bayesian opt...

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30th International Symposium on Semiconductor Manufacturing, ISSM 2024

作者： Kinoshita, Shigeru Inoue, Yuta Watanabe, Tetsuro Ikeda, Kosuke Nishio, Seiwa Teruya, Atsushi Sakai, Naoki Goda, Takashi Kioxia Corporation Frontier Technology R and D Institute Yokohama-shi Japan Kioxia Corporation Advanced Memory Development Center Yokkaichi-shi Japan The University of Tokyo Graduate School of Engineering Bunkyo-ku Japan

ISBN: (纸本)9798331510589

In this study, we propose a space-filling Latin hypercube design with small fill distance and large separation radius based on simulated annealing for efficient Bayesian optimization. Through an example focused on optimizing high aspect ratio hole etching, we demonstrate that initial sampling with the proposed design is advantageous compared to conventional designs in terms of the convergence of Bayesian optimization with fewer experiments. © 2024 IEEE.

关键词： Aspect ratio

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Optimal Design of Wet Etching Bath for 3D Flash Memories Using Multi-Objective Bayesian Optimization

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IEEE Transactions on Semiconductor Manufacturing 2025年

作者： Kouda, Miyuki Mori, Yumi Sugita, Tomohiko Ng, Youyang KIOXIA Corporation AI and System Research Center Frontier Technology R and D Institute Japan KIOXIA Corporation Advanced Memory Process Development Center Memory Division Japan

Recently, the complexity of semiconductor manufacturing processes has increased, resulting in a growing need for high-precision optimization of device structures. For example, in batch-type wet etching devices, the flow of chemical liquids in the process bath can vary depending on the device structure, which causes variations in the etching state of the wafer. This issue is addressed using a feedback mechanism that adjusts the device structure iteratively based on the results of an etching experiment, thereby achieving more uniform etching conditions. However, this approach requires a large number of trial experiments. In the fabrication process of 3D flash memory devices, the formation of word lines in the silicon substrate requires precise control of the silicon concentration in the etching solution. However, this concentration can fluctuate due to the dissolution of the SiN film during the etching process, which can cause various problems. Thus, this study proposes an innovative multi-objective Bayesian optimization method that is informed by image and physical quantity data from fluid dynamics simulations to derive optimal wet etching bath design parameters. The proposed method was validated through simulation experiments, and the simulation results were used to identify the best possible wet etching bath designs. © 1988-2012 IEEE.

关键词： Wet etching

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