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Dynamic neural network with memristive CIM and CAM for 2D and 3D vision

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arXiv 2024年

作者： Zhang, Yue Zhang, Woyu Wang, Shaocong Lin, Ning Yu, Yifei He, Yangu Wang, Bo Jiang, Hao Lin, Peng Xu, Xiaoxin Qi, Xiaojuan Wang, Zhongrui Zhang, Xumeng Shang, Dashan Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100049 China ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong Institute of the Mind The University of Hong Kong Hong Kong Key Lab of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing100049 China State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai200433 China University of Chinese Academy of Sciences Beijing100049 China College of Computer Science and Technology Zhejiang University Zhejiang310027 China Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong

The brain is dynamic, associative and efficient. It reconfigures by associating the inputs with past experiences, with fused memory and processing. In contrast, AI models are static, unable to associate inputs with past experiences, and run on digital computers with physically separated memory and processing. We propose a hardware-software co-design, a semantic memory-based dynamic neural network (DNN) using memristor. The network associates incoming data with the past experience stored as semantic vectors. The network and the semantic memory are physically implemented on noise-robust ternary memristor-based Computing-In-Memory (CIM) and Content-Addressable Memory (CAM) circuits, respectively. We validate our co-designs, using a 40nm memristor macro, on ResNet and PointNet++ for classifying images and 3D points from the MNIST and ModelNet datasets, which not only achieves accuracy on par with software but also a 48.1% and 15.9% reduction in computational budget. Moreover, it delivers a 77.6% and 93.3% reduction in energy consumption. © 2024, CC BY.

关键词： Memristors

A Ka-Band High-Gain and Wideband mmW Down-Conversion Mixer for 5G Communication Applications 15

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A Ka-Band High-Gain and Wideband mmW Down-Conversion Mixer f...

15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020

作者： Bao, Rongsheng Rao, Shengyu Shi, Chunqi Chen, Jinghong Chen, Guangsheng Zhang, Runxi Institute of Microelectronic Circuits and Systems East China Normal University Shanghai200241 China University of Houston Department of Electrical and Computer Engineering Houston77004 United States Shanghai Eastsoft Microelectronics Co. Ltd. Shanghai200235 China

ISBN: (纸本)9781728162355

This paper implements a high-gain and wideband CMOS mmW down-conversion mixer for 5G communication applications. A parallel inductor is exploited to eliminate the parasitic capacitance between the transconductance transistors and the switching transistors. The dynamic current injection (DCI) method based on the cross-coupled transistors is proposed to realize the negative resistance to cancel the loss resistance, which is introduced by the parallel inductor, and then the gain is improved while the noise is reduced. A resonating peak control (RPC) technology based on the passive transformer is utilized to improve bandwidth. The chip is designed using 40-nm CMOS process and the simulated peak conversion gain (CG) is 16.78 dB at 26 GHz. The 3 dB bandwidth is from 24 to 30 GHz. The minimum noise figure (NF) is 9.65 dB and the input P1dB is-11 dBm. The DC power consumption is 16 mW. © 2020 IEEE.

关键词： Capacitance

A Character Recognition Method for Chip Surface Characters Based on Text Replacement

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SSRN

SSRN 2022年

作者： Xu, Wei Shi, Yecun Xi, Yu Liu, Jingyue Wang, Tan Zhang, Haichao Guo, Cuijuan Bai, Jinjun Xu, Degang Yao, Jianquan Tianjin Key Laboratory of Optoelectronic Detection Technology and Systems School of Electronic and Information Engineering Tiangong University Tianjin300387 China Microelectronic Device Reliability Laboratory Research Test Center of Defense Technology for Aerospace Science and Industry Beijing100854 China Department of Electrical and Computer Engineering Northeatern University BostonMA02115 United States School of Precision Instruments and Optoelectronics Engineering Institute of Laser and Optoelectronics Tianjin University Tianjin300072 China

Due to the particular screen printing rules defined by the unique chip manufacturer and the huge variety of chips, it is difficult to identify chip information by naked eye in chip reliability detection. Automatic identification character technology can help us obtain the information of the chip. But the special character samples in the dataset is extremely uneven. When recognizing characters on chip surface by deep learning, the limited certain characters dataset will reduce the recognition accuracy. A character recognition method for chip surface characters based on text replacement is proposed in this paper. Firstly, the efficient channel attention modules are added to enhance the feature extraction of characters in the text style transfer process. Secondly, the dilated convolution layers are used to replace the residual module during the background restoration process, which help to obtain a more comprehensive background texture feature. Finally, a one-stage target detection network YOLOv5s is used to detect the characters on the chip surface. The experimental results demonstrated that the three evaluation metrics for image generation quality (l2 error, psnr, and ssim) achieved better performance than previous work due to the text replacement network. The overall charac- © 2022, The Authors. All rights reserved.

关键词： Convolution

A Character Recognition Method for Chip Surface Characters Based on Text Replacement

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SSRN

SSRN 2022年

关键词： Convolution

Continuous-Time Digital Twin with Analogue Memristive Neural Ordinary Differential Equation Solver

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arXiv 2024年

作者： Chen, Hegan Yang, Jichang Chen, Jia Wang, Songqi Wang, Shaocong Wang, Dingchen Tian, Xinyu Yu, Yifei Chen, Xi Lin, Yinan He, Yangu Wu, Xiaoshan Li, Yi Zhang, Xinyuan Lin, Ning Xu, Meng Li, Yi Zhang, Xumeng Wang, Zhongrui Wang, Han Shang, Dashan Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong Institute of the Mind The University of Hong Kong Hong Kong Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China University of Chinese Academy of Sciences Beijing100049 China School of Integrated Circuits Hubei Key Laboratory for Advanced Memories Huazhong University of Science and Technology Wuhan430074 China State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai200433 China Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong

Digital twins, the cornerstone of Industry 4.0, replicate real-world entities through computer models, revolutionising fields such as manufacturing management and industrial automation. Recent advances in machine learning provide data-driven methods for developing digital twins using discrete-time data and finite-depth models on digital computers. However, this approach fails to capture the underlying continuous dynamics and struggles with modelling complex system behaviour. Additionally, the architecture of digital computers, with separate storage and processing units, necessitates frequent data transfers and Analogue-Digital (A/D) conversion, thereby significantly increasing both time and energy costs. Here, we introduce a memristive neural ordinary differential equation (ODE) solver for digital twins, which is capable of capturing continuous-time dynamics and facilitates the modelling of complex systems using an infinite-depth model. By integrating storage and computation within analogue memristor arrays, we circumvent the von Neumann bottleneck, thus enhancing both speed and energy efficiency. We experimentally validate our approach by developing a digital twin of the HP memristor, which accurately extrapolates its nonlinear dynamics, achieving a 4.2-fold projected speedup and a 41.4-fold projected decrease in energy consumption compared to state-of-the-art digital hardware, while maintaining an acceptable error margin. Additionally, we demonstrate scalability through experimentally grounded simulations of Lorenz96 dynamics, exhibiting projected performance improvements of 12.6-fold in speed and 189.7-fold in energy efficiency relative to traditional digital approaches. By harnessing the capabilities of fully analogue computing, our breakthrough accelerates the development of digital twins, offering an efficient and rapid solution to meet the demands of Industry 4.0. © 2024, CC BY-NC-SA.

关键词： Energy utilization

GaAs/GeSn/Ge n–i–p diodes and light emitting diodes formed via grafting

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Journal of Vacuum Science & Technology B

Journal of Vacuum Science & Technology B 2024年第4期42卷

作者： Jie Zhou Haibo Wang Po Rei Huang Shengqiang Xu Yang Liu Jiarui Gong Jianping Shen Daniel Vicent Samuel Haessly Alireza Abrand Parsian K. Mohseni Munho Kim Shui-Qing Yu Guo-En Chang Xiao Gong Zhenqiang Ma Department of Electrical and Computer Engineering University of Wisconsin—Madison Madison Wisconsin 53706 Department of Electrical and Computer Engineering National University of Singapore Singapore 117576 Singapore Department of Mechanical Engineering and Advanced Institute of Manufacturing with High-tech Innovations National Chung Cheng University Chiayi County 62102 Taiwan Department of Electrical and Microelectronic Engineering Rochester Institute of Technology Rochester New York 14623 School of Electrical and Electronic Engineering Nanyang Technological University 50 Nanyang Avenue Singapore 639798 Singapore Department of Electrical Engineering University of Arkansas Fayetteville Arkansas 72701

Germanium-tin (GeSn) is a promising semiconductor material for future optoelectronic devices operating at the near-infrared to mid-infrared spectral range. In this work, we report the synthesis and characterization of a GaAs/GeSn-MQW/Ge n–i–p heterojunction created via grafting. The improved energy barriers between GaAs and GeSn-MQW enable the diodes fabricated from the heterojunction to exhibit extraordinary rectification ratios (larger than 105) and record-low reverse-bias current density (∼10−6 A/cm2). The grafting-based LED performs as well as the epitaxially grown counterpart. The work may pave the way for future improvements of GeSn-based electronic devices.

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Pruning random resistive memory for optimizing analogue AI

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arXiv 2023年

作者： Li, Yi Wang, Songqi Zhao, Yaping Wang, Shaocong Zhang, Woyu He, Yangu Lin, Ning Cui, Binbin Chen, Xi Zhang, Shiming Jiang, Hao Lin, Peng Zhang, Xumeng Qi, Xiaojuan Wang, Zhongrui Xu, Xiaoxin Shang, Dashan Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong State Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Frontier Institute of Chip and System Fudan University Shanghai200433 China College of Computer Science and Technology Zhejiang University Zhejiang310027 China Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong University of Chinese Academy of Sciences Beijing100049 China Institute of Mind The University of Hong Kong Hong Kong

The rapid advancement of artificial intelligence (AI) has been marked by the large language models exhibiting human-like intelligence. However, these models also present unprecedented challenges to energy consumption and environmental sustainability, which are exacerbated by the increasing number of users and the development of even larger models. One promising solution is to revisit analogue computing, a technique that predates digital computing and exploits emerging analogue electronic devices, such as resistive memory, which features in-memory computing, high scalability, and nonvolatility that addresses the von Neumann bottleneck, slowdown of Moore’s law, and volatile DRAM of conventional digital hardware. However, analogue computing still faces the same challenges as before: programming nonidealities and expensive programming due to the underlying devices physics. Therefore, leveraging the efficiency advantage while mitigating the programming disadvantage of analogue computing with resistive memory is a major open problem in AI hardware and electronics communities. Here, we report a universal solution, software-hardware co-design using structural plasticity-inspired edge pruning to optimize the topology of a randomly weighted analogue resistive memory neural network. Software-wise, the topology of a randomly weighted neural network is optimized by pruning connections rather than precisely tuning resistive memory weights. Hardware-wise, we reveal the physical origin of the programming stochasticity using transmission electron microscopy, which is leveraged for large-scale and low-cost implementation of an overparameterized random neural network containing high-performance sub-networks. We implemented the co-design on a 40nm 256K resistive memory macro, observing 17.3% and 19.9% accuracy improvements in image and audio classification on FashionMNIST and Spoken digits datasets, as well as 9.8% (2%) improvement in PR (ROC) in image segmentation on DRIVE datasets, r

关键词： Energy utilization

Resistive Memory-based Neural Differential Equation Solver for Score-based Diffusion Model

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arXiv 2024年

作者： Yang, Jichang Chen, Hegan Chen, Jia Wang, Songqi Wang, Shaocong Yu, Yifei Chen, Xi Wang, Bo Zhang, Xinyuan Cui, Binbin Li, Yi Lin, Ning Xu, Meng Li, Yi Xu, Xiaoxin Qi, Xiaojuan Wang, Zhongrui Zhang, Xumeng Shang, Dashan Wang, Han Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering the University of Hong Kong Hong Kong ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai200433 China Institute of the Mind the University of Hong Kong Hong Kong University of Chinese Academy of Sciences Beijing100049 China School of Integrated Circuits Hubei Key Laboratory for Advanced Memories Huazhong University of Science and Technology Wuhan430074 China Department of Electronic and Computer Engineering the Hong Kong University of Science and Technology Hong Kong

Human brains image complicated scenes when reading a novel. Replicating this imagination is one of the ultimate goals of AI-Generated Content (AIGC). However, current AIGC methods, such as score-based diffusion, are still deficient in terms of rapidity and efficiency. This deficiency is rooted in the difference between the brain and digital computers. Digital computers have physically separated storage and processing units, resulting in frequent data transfers during iterative calculations, incurring large time and energy overheads. This issue is further intensified by the conversion of inherently continuous and analog generation dynamics, which can be formulated by neural differential equations, into discrete and digital operations. Inspired by the brain, we propose a time-continuous and analog in-memory neural differential equation solver for score-based diffusion, employing emerging resistive memory. The integration of storage and computation within resistive memory synapses surmount the von Neumann bottleneck, benefiting the generative speed and energy efficiency. The closed-loop feedback integrator is time-continuous, analog, and compact, physically implementing an infinite-depth neural network. Moreover, the software-hardware co-design is intrinsically robust to analog noise. We experimentally validate our solution with 180 nm resistive memory in-memory computing macros. Demonstrating equivalent generative quality to the software baseline, our system achieved remarkable enhancements in generative speed for both unconditional and conditional generation tasks, by factors of 64.8 and 156.5, respectively. Moreover, it accomplished reductions in energy consumption by factors of 5.2 and 4.1. Our approach heralds a new horizon for hardware solutions in edge computing for generative AI applications. © 2024, CC BY-NC-SA.

关键词： Diffusion

Efficient and accurate neural field reconstruction using resistive memory

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arXiv 2024年

作者： Yu, Yifei Wang, Shaocong Zhang, Woyu Zhang, Xinyuan Wu, Xiuzhe He, Yangu Yang, Jichang Zhang, Yue Lin, Ning Wang, Bo Chen, Xi Wang, Songqi Zhang, Xumeng Qi, Xiaojuan Wang, Zhongrui Shang, Dashan Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong Hong Kong ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong Hong Kong Institute of Mind The University of Hong Kong Hong Kong Hong Kong Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China University of Chinese Academy of Sciences Beijing100049 China Frontier Institute of Chip and System Fudan University Shanghai200433 China Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong Hong Kong

Human beings construct perception of space by integrating sparse observations into massively interconnected synapses and neurons, offering a superior parallelism and efficiency. Replicating this capability in AI finds wide applications in medical imaging, AR/VR, and embodied AI, where input data is often sparse and computing resources are limited. However, traditional signal reconstruction methods on digital computers face both software and hardware challenges. On the software front, difficulties arise from storage inefficiencies in conventional explicit signal representation. Hardware obstacles include the von Neumann bottleneck, which limits data transfer between the CPU and memory, and the limitations of CMOS circuits in supporting parallel processing. We propose a systematic approach with software-hardware co-optimizations for signal reconstruction from sparse inputs. Software-wise, we employ neural field to implicitly represent signals via neural networks, which is further compressed using low-rank decomposition and structured pruning. Hardware-wise, we design a resistive memory-based computing-in-memory (CIM) platform, featuring a Gaussian Encoder (GE) and an MLP Processing Engine (PE). The GE harnesses the intrinsic stochasticity of resistive memory for efficient input encoding, while the PE achieves precise weight mapping through a Hardware-Aware Quantization (HAQ) circuit. We demonstrate the system’s efficacy on a 40nm 256Kb resistive memory-based in-memory computing macro, achieving 31.5×, 35.5×, and 47.2× energy efficiency improvements and 10.8×, 38.8×, and 6.2× parallelism improvements without compromising reconstruction quality in tasks like 3D CT sparse reconstruction, novel view synthesis, and novel view synthesis for dynamic scenes. This work advances the AI-driven signal restoration technology and paves the way for future efficient and robust medical AI and 3D vision applications. Copyright © 2024, The Authors. All rights reserved.

关键词： Signal reconstruction