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A Ka band FMCW Transmitter with a High Ratio Multiplier

A Ka band FMCW Transmitter with a High Ratio Multiplier

引用

International SoC Design Conference, ISOCC

作者： Junho Moon Sukwon Kang Dongyeol Yang Byung-Sung Kim Department of Electrical and Computer Engineering RF Microelectronic Design Lab College of Information and Communication EngineeringSungkyunkwan University Suwon South Kore

ISBN: (纸本)9781665459723

This work presents a Ka band FMCW transmitter equipped with a high ratio frequency multiplier, which can be easily driven by the DDS (Direct Digital Synthesis) without PLLs. The transmitter is composed of a two-stage x35 frequency multiplier and a two-stage power amplifier (PA). The first stage of the frequency multiplier is a 5-phase ring-VCO-based injection locked frequency multiplier with a ratio of 7. The second stage is a 5-push frequency multiplier combining the 5-phase outputs of the ring cells in the first stage. The final output of 35 GHz is amplified by the transformer coupled two-stage amplifier which provides the output power of 14.1 dBm. The total power consumption is 309.56mW and 1GHz offset spur is lower than 24dBc. Measured phase noise at 35GHz at 1MHz offset is - 103.3dBc/Hz.

关键词： Ring oscillators Phase noise Tracking loops Power demand Phase measurement Transmitters Power amplifiers

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Absolute longitudinal distance measurement verification of a standard polystyrene nanoparticle near a surface in water by means of multi-wavelength evanescent field 22

Absolute longitudinal distance measurement verification of a...

引用

22nd International Conference of the European Society for Precision engineering and Nanotechnology, EUSPEN 2022

作者： Blattler, Aran Khajornrungruang, Panart Suzuki, Keisuke Baba, Akiyoshi Goto, Daiki Graduate School of Computer Science and System Engineering Mechanical Information Science and Technology Course Kyushu Institute of Technology Fukuoka Japan Department of Intelligent and Control Systems Advanced Mechanical Division Kyushu Institute of Technology Fukuoka Japan Center of Microelectronic System Kyushu Institute of Technology Fukuoka Japan School of Computer Science and System Engineering Advanced Mechanical Course Kyushu Institute of Technology Fukuoka Japan

ISBN: (纸本)9781998999118

In the wet semiconductor process, abrasive nanoparticles are widely used in the chemical mechanical polishing (CMP) process to polish wafer surfaces for high planarization. During polishing, nanoparticles move with a high-speed three-dimensional (3D) position in the solution. In the 3D particles's moving positions, Z is a perpendicular longitudinal distance between the surface to the nanoparticle that plays a significant role in polishing, which could not be measured by general microscopy without longitudinal scanning. To understand nanoparticle phenomena near-surface, we have proposed and developed the apparatus with real-time fastmotion tracking on optical multi-wavelength evanescent fields microscopy to measure the 3D motion of the nanoparticle in water without scanning. In euspen's 2020, we could verify the relative distance ?Z of nanoparticles in water, but the absolute distance Z is unknown yet. In this manuscript, we have therefore developed an invisible nano-step height in water to verify the absolute height Z of an individual nanoparticle. The invisible nano-step height in water is made from an optical resin with a refractive index of 1.35 that is close to a refractive index of water to avoid unnecessary light during experimental verification. The nano-step height was less than 100 nm on a glass surface, fabricated using nanoimprint lithography. Polystyrene f100 nm standard particles in water were used to verify the height Z. The results of height Z of nanoparticles could be measured less than 100 nm with the measurement uncertainty ±10 nm (2s), which is related to the interferometer result of the nano-step height. © European Society for Precision engineering and Nanotechnology, Conference Proceedings - 22nd International Conference and Exhibition, EUSPEN 2022. All rights reserved.

关键词： Nanoparticles

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±45° Dual-Polarization Multi-beam Meta-surface Lens Antenna

±45° Dual-Polarization Multi-beam Meta-surface Lens Antenn...

引用

2021 IEEE International Symposium on Antennas and Propagation and North American Radio Science Meeting, APS/URSI 2021

作者： Luo, Yu Zhao, Songjiang Chen, Zhi Ning School of Microelectronics Tianjin University Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology Tianjin China National University of Singapore Department of Electric and Computer Engineering Singapore Singapore

This paper presents a metasurface lens antenna fed by a 2×5 planar ±45° dual-polarization patch antenna array which is lightweight and low-complexity. The designed antenna can cover the 5.8 GHz band and... 详细信息

ISBN: (纸本)9781728146706

关键词： Lens antennas

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Slow light engineering in the hollow-core vertical photonic crystal waveguide for gas sensing

Slow light engineering in the hollow-core vertical photonic ...

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CLEO: Applications and Technology, A and T 2022

作者： Rostamian, Ali Midkiff, Jason Yoo, Kyoung Min Chen, Ray T. Microelectronic Research Center Department of Electrical and Computer Engineering University of Texas at Austin AustinTX78758 United States Omega Optics Inc. 8500 Shoal Creek Blvd. Bldg. 4 Suite 200 AustinTX78757 United States

In this paper, we present a hollow-core vertical photonic crystal waveguide geometry in silicon for gas detection in the mid-infrared region. The dispersion is engineered to enhance light-matter interactions inside th... 详细信息

ISBN: (纸本)9781957171050

关键词： Photonic crystals

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Object Acquizition of Stationary and Moving Targets

Object Acquizition of Stationary and Moving Targets

引用

International Conference on Modern Problems of Radio engineering, Telecommunications and computer Science

作者： Myroslav Riabyi Sergey Edward Lyshevski Roman Odarchenko Faculty of Computer Sciences and Technologies National Aviation University Kyiv Ukraine Department of Electrical and Microelectronic Engineering Rochester Institute of Technology Rochester NY USA Faculty of Air Navigation Electronics and Telecommunications National Aviation University Kyiv Ukraine

ISBN: (数字)9798331520564

ISBN: (纸本)9798331520571

This paper studies near real time obj ect acquisition by means of detection, identification and engagement on stationary, moving and maneuvering targets in the air and land domains. Using the streamed videos from monochrome and color cameras, a machine vision concept accomplishes object detection by recognizing the object-specific edges and shapes which yield unique geometric features. Object recognition with descriptive identification at reasonable accuracy is performed using the Jaccard index. The region proposal detectors with the intersection over union is implemented by a convolutional neural network. The machine learning models, implemented by the low power system-on-module, were trained. These machine learning algorithms and models support feature detection and matching, localization, and, three-dimensional spatiotemporal reconstruction. The two-and three-dimensional geometry with object and background contrast and color mappings are considered. Subsequent tracking and locking on maneuverable targets is performed using spatio-temporal three-dimensional analytics. The airborne machine acquisition module with trained models is demonstrated. A concept suits monochrome, color and thermal analog and digital cameras. Experiments in typified operational environments demonstrate acceptable accuracy, convergence, low latency and near real-time capabilities for different object categories and classes within developed custom datasets.

关键词： Accuracy Target tracking Atmospheric modeling Color Machine learning Real-time systems Thermal analysis Telecommunications Object recognition Videos

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A 74.8-88.8 GHz Wideband CMOS LNA Achieving +4.73 dBm OP1dB and 6.39 dB Minimum NF

A 74.8-88.8 GHz Wideband CMOS LNA Achieving +4.73 dBm OP1dB ...

引用

Microwave, MTT-S International Symposium

作者： Linfeng Zou Kangjie Zhao Zonghua Fang Leilei Huang Boxiao Liu Chunqi Shi Guangsheng Chen Jinghong Chen Runxi Zhang Institute of Microelectronic Circuits and Systems East China Normal University China Shanghai Eastsoft Microelectronics Co. Ltd. China Department of Electrical and Computer Engineering University of Houston USA

This paper presents a 74.8-88.8 GHz low-noise amplifier (LNA) in a 55-nm CMOS technology. The LNA employs one common-gate (CG) stage, one common-source (CS) stage, and two cascode stages. A hybrid broadband interstage network (HBIN) is developed to extend the amplifier bandwidth. An inductor-feedback common-gate-shorting (IFCGS) technique is proposed to improve the gain and output 1dB compression point (OP1dB). An out-of-phase-dual-coupling (OPDC) transformer structure is also developed to achieve g m -boost and reduce the noise of the CG stage. Benefiting from the proposed techniques, the LNA achieves a measured -3dB bandwidth of 14 GHz, a 17.1 dB peak gain, a minimum noise figure of 6.39 dB, and 4.73 dBm OP1dB at 80 GHz while consuming 72.4 mW of power.

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UVM Verification IP for AXI

UVM Verification IP for AXI

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2021 IEEE East-West Design and Test Symposium, EWDTS 2021

作者： Melikyan, Vazgen Harutyunyan, Stepan Kirakosyan, Artak Kaplanyan, Taron National Polytechnic University of Armenia Chair of Microelectronic Circuits and Systems Synopsys Armenia Educational Department Yerevan Armenia University of Ottawa School of Electrical Engineering and Computer Science Ottawa Canada

ISBN: (纸本)9781665445030

Over time, the complexity of ICs design increasing which making these designs more error-prone. Verification of Integrated Circuits using Verilog lacks the flexibility and reusability of the environment. System Verilog UVM methodology gives building blocks and OOP concepts to work with. That allows to create much more flexible test environment with reusable components. This paper presents a verification architecture of configurable Verification IP for AXI interface. This paper presents an architecture of verification environment for AMBA AXI interface and can be used to test any AXI device. A functional coverage model has been developed to determine if the verification process covers all possible scenarios or not. Each testcase reports coverage which is later used to analyze the effectiveness of the testcase. Full coverage has been achieved using both random and directed test cases. The coding is done using System Verilog and the simulation is done using VCS. © 2021 IEEE.

关键词： Reusability

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SEE-MCAM: Scalable Multi-Bit FeFET Content Addressable Memories for Energy Efficient Associative Search

SEE-MCAM: Scalable Multi-Bit FeFET Content Addressable Memor...

引用

IEEE International Conference on computer-Aided Design

作者： Shengxi Shou Che-Kai Liu Sanggeon Yun Zishen Wan Kai Ni Mohsen Imani X. Sharon Hu Jianyi Yang Cheng Zhuo Xunzhao Yin College of Information Science and Electronic Engineering Zhejiang University China Department of Information and Computer Science University of California Irvine USA School of Electrical and Computer Engineering Georgia Institute of Technology USA Department of Electrical and Microelectronic Engineering Rochester Institute of Technology USA Department of Computer Science and Engineering University of Notre Dame USA School of Micro-Nano Electronics. Zhejiang University China Key Laboratory of Collaborative Sensing and Autonomous Unmaned Systems of Zhejiang Province China

Artificial intelligence has made remarkable advancements in recent years, leading to the development of algorithms and models capable of handling ever-increasing amounts of data. The computational demands of these algorithms necessitate circuit and architecture designs that go beyond the von-Neumann paradigm. Content addressable memories (CAMs), which implement parallel associative search functionality within memory blocks to overcome the memory wall bottleneck, have proven to be effective for data-intensive tasks. While current CAM designs have achieved higher storage density and energy efficiency than their CMOS-based counterparts by leveraging emerging non-volatile memories (NVM), most of these implementations are limited to binary storage cells. In this work, we propose SEE-MCAM, scalable and compact multi-bit CAM (MCAM) designs that utilize the three-terminal ferroelectric FET (FeFET) as the proxy. By exploiting the multi-level-cell characteristics of FeFETs, our proposed SEE-MCAM designs enable multi-bit associative search functions and achieve better energy efficiency and performance than existing FeFET-based CAM designs. We validated the functionality of our proposed designs by achieving 3 bits per cell CAM functionality, resulting in 3x improvement in storage density. The area per bit of the proposed SEE-MCAM cell is 8% of the conventional CMOS CAM. We thoroughly investigated the scalability and robustness of the proposed design. Evaluation results suggest that the proposed 2FeFET-1 T SEE-MCAM achieves 9.8× more energy efficiency and 1.6× less search latency compared to the CMOS CAM, respectively. When compared to existing MCAM designs, the proposed SEE-MCAM can achieve 8.7× and 4.9× more energy efficiency than ReRAM-based and FeFET-based MCAMs, respectively. Benchmarking results show that our approach provides up to 3 orders of magnitude improvement in speedup and energy efficiency over a GPU implementation in accelerating a novel quantized hyperdimensiona

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Design and Verification of Novel Sync Cell

Design and Verification of Novel Sync Cell

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2021 IEEE East-West Design and Test Symposium, EWDTS 2021

作者： Melikyan, Vazgen Harutyunyan, Stepan Kaplanyan, Taron Kirakosyan, Artak Momjyan, Arsen Amiryan, Vardan University of Armenia Chair of Microelectronic Circuits and Systems National Polytechnic Synopsys Armenia Educational Department Yerevan Armenia University of Ottawa School of Electrical Engineering and Computer Science Ottawa Canada

ISBN: (纸本)9781665445030

A novel approach of clock domain crossing solution is presented. For high-frequency conditions traditional approach calls for multiple D-flops for single bit synchronization. The higher the frequency the higher the number of flops. In high-frequency solutions, such an approach can consume much-needed space and limit the useful area for additional logic. Hence a new mixed-signal circuit is introduced which can be used in high-frequency applications to reduce the overall area of synchronizer logic used for single-bit synchronization. Comparison has been done for traditional multi-flop synchronization and proposed design with analog comparators. Unlike traditional design, the proposed circuit has no additional delays in form of additional clock cycles. For the usual use case of a two-stage synchronizer, the proposed design has 20% more area, but in high-frequency applications, where three or more synchronization stages are used, at least 30% are reduction was achieved (the higher the stage number, the more reduction percentage). The simulation was performed with SAED 32/28 nm technology. © 2021 IEEE.

关键词： Synchronization

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6-bit CMOS phase shifter and attenuator based on time-modulation for Ku-band phased array applications

6-bit CMOS phase shifter and attenuator based on time-modula...

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IEEE National Conference on Radar

作者： Shiwei Wu Hongliang Zhao Chong He Dongwei Pang Yan Wang Qi Xia Zongming Duan School of Microelectronic University of Science and Technology of China East China Research Institute of Electronic Engineering Hefei China Department of Microelectronic East China Research Institute of Electronic Engineering Hefei China School of Electronic Information and Electric Engineerin Shanghai Jiao Tong University Shanghai China School of Information Science and Technology University of Science and Technology of China Hefei China School of Microelectronic University of Science and Technology of China Hefei China Department of Electrical and Computer Engineering University of Texas at San Antonio San Antonio USA

Quasi-single sideband time modulation (QSSB-TM) topology is adopted to design high precision 6-bit phase and amplitude circuit in 0.13-um CMOS technology. The excellent amplitude and phase performance are realized with QSSB-TM circuit composed of a 90° power divider, two 180°phase shifters and a 0°Wilkinson power divider in 14-18GHz. The max root mean square (RMS) phase error is 0.2° in the 6-bit phase shifter mode. The max RMS amplitude error is 0.63dB in the 6-bit attenuator mode. The chip size is $\boldsymbol{1.5}\mathbf{mm}^{*}\boldsymbol{1.7}\mathbf{mm}(\boldsymbol{2.55}\mathbf{mm}^{2})$ .

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