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Prior-Boosted GRL: Microarchitecture Design Space Exploration via Graph Representation Learning

IEEE Transactions on Computer-Aided Design of Integrated circuits and systems 2025年第3期44卷 1141-1154页

作者： Wu, Zheng Shen, Jinyi Yi, Xiaoling Shang, Li Yang, Fan Zeng, Xuan Fudan University State Key Laboratory of Integrated Circuits and Systems The School of Microelectronics Shanghai200433 China Fudan University State Key Laboratory of Integrated Circuits and Systems Shanghai200433 China KU Leuven Department of Electrical Engineering Microelectronics Circuits and Systems Leuven3000 Belgium Fudan University State Key Laboratory of Integrated Circuits and Systems The School of Computer Science Shanghai200433 China

The design space exploration (DSE) of contemporary microprocessors faces a significant challenge of high-computational cost. In this context, we introduce Prior-boosted graph representation learning (GRL), a novel framework for the DSE of the microarchitectures the microprocessors underpinned by graph embeddings. Using GRL, Prior-boosted GRL constructs a compact and continuous vector space for design representation. This framework is further boosted by an efficient sampling algorithm informed by prior knowledge, which is instrumental in generating a superior set of initial designs to accelerate the exploration process. A well-designed ensemble surrogate model is combined with the multiobjective Bayesian optimization to explore the design space holistically within this graph-embedding domain. Rigorous experimental evaluations conducted on the RISC-V Berkeley-Out-of-Order Machine (BOOM) platform demonstrate that Prior-boosted GRL substantially surpasses preceding methods, achieving a 107.79% enhancement in Pareto front quality compared to the state-of-the-art DSE algorithm. It also outstrips manual designs on performance, power, and area metrics. As of this writing, Prior-boosted GRL holds the first place in the ICCAD 2022 CAD Contest evaluation platform. © 2024 IEEE.

关键词： Graph embeddings

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Low Stress TSV Arrays for High-Density Interconnection

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engineering 2024年第7期38卷 201-208页

作者： Binbin Jiao Jingping Qiao Shiqi Jia Ruiwen Liu Xueyong Wei Shichang Yun Yanmei Kong Yuxin Ye Xiangbin Du Lihang Yu Bo Cong Institute of Microelectronics Chinese Academy of SciencesBeijing 100000China School of Integrated Circuits University of Chinese Academy of SciencesBeijing 100000China State Key Laboratory for Manufacturing Systems Engineering Xi’an Jiaotong UniversityXi’an 710049China

In three-dimensional(3D)stacking,the thermal stress of through-silicon via(TSV)has a significant influence on chip performance and reliability,and this problem is exacerbated in high-density TSV *** this study,a novel hollow tungsten TSV(W-TSV)is presented and *** hollow structure provides space for the release of thermal *** results showed that the hollow W-TSV structure can release 60.3%of thermal stress within the top 2 lm from the surface,and thermal stress can be decreased to less than 20 MPa in the radial area of 3 *** ultra-high-density(1600 TSV∙mm2)TSV array with a size of 640×512,a pitch of 25 lm,and an aspect ratio of 20.3 was fabricated,and the test results demonstrated that the proposed TSV has excellent electrical and reliability *** average resistance of the TSV was 1.21 *** leakage current was 643 pA and the breakdown voltage was greater than 100 *** resistance change is less than 2%after 100 temperature cycles from40 to 125℃.Raman spectroscopy showed that the maximum stress on the wafer surface caused by the hollow W-TSV was 31.02 MPa,which means that there was no keep-out zone(KOZ)caused by the TSV *** results indicate that this structure has great potential for applications in large-array photodetectors and 3D integrated circuits.

关键词： Thermal stress Through-silicon via(TSV)High-density integration

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InGaZnO-based photoelectric synaptic devices for neuromorphic computing

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Journal of Semiconductors 2024年第9期45卷 42-47页

作者： Jieru Song Jialin Meng Tianyu Wang Changjin Wan Hao Zhu Qingqing Sun David Wei Zhang Lin Chen School of Microelectronics State Key Laboratory of Integrated Chips and SystemsFudan UniversityShanghai 200433China School of Integrated Circuits Shandong UniversityJinan 250100China National Integrated Circuit Innovation Center Shanghai 201203China School of Electronic Science and Engineering Nanjing UniversityNanjing 210023China Jiashan Fudan Institute Jiashan 314102China

Photoelectric synaptic devices could emulate synaptic behaviors utilizing photoelectric effects and offer promising prospects with their high-speed operation and low crosstalk. In this study, we introduced a novel InGaZnO-based photoelectric memristor. Under both electrical and optical stimulation, the device successfully emulated synaptic characteristics including excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF), long-term potentiation (LTP), and long-term depression (LTD). Furthermore, we demonstrated the practical application of our synaptic devices through the recognition of handwritten digits. The devices have successfully shown their ability to modulate synaptic weights effectively through light pulse stimulation, resulting in a recognition accuracy of up to 93.4%. The results illustrated the potential of IGZO-based memristors in neuromorphic computing, particularly their ability to simulate synaptic functionalities and contribute to image recognition tasks.

关键词： InGaZnO artificial synapse neuromorphic computing photoelectric memristor

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Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement 24

Physically Aware Synthesis Revisited: Guiding Technology Map...

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43rd International Conference on Computer-Aided Design, ICCAD 2024

作者： Pan, Hongyang Lan, Cunqing Liu, Yiting Wang, Zhiang Shang, Li Zeng, Xuan Yang, Fan Zhu, Keren State Key Lab of Integrated Circuits and Systems School of Microelectronics Fudan University China School of Computer Science Fudan University China Department of Electrical and Computer Engineering University of California San Diego United States

ISBN: (纸本)9798400710773

A typical VLSI design flow is divided into separated front-end logic synthesis and back-end physical design (PD) stages, which often require costly iterations between these stages to achieve design closure. Existing approaches face significant challenges, notably in utilizing feedback from physical metrics to better adapt and refine synthesis operations, and in establishing a unified and comprehensive metric. This paper introduces a new Primitive logic gate placement guided technology MAPping (PigMAP) framework to address these challenges. With approximating technology-independent spatial information, we develop a novel wirelength (WL) driven mapping algorithm to produce PD-friendly netlists. PigMAP is equipped with two schemes: a performance mode that focuses on optimizing the critical path WL to achieve high performance, and a power mode that aims to minimize the total WL, resulting in balanced power and performance outcomes. We evaluate our framework using the EPFL benchmark suites with ASAP7 technology, using the OpenROAD tool for place-and-route. Compared with OpenROAD flow scripts, performance mode reduces delay by 14% while increasing power consumption by only 6%. Meanwhile, power mode achieves a 3% improvement in delay and a 9% reduction in power consumption. © 2024 Copyright is held by the owner/author(s).

关键词： Logic design

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ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Synthesis

ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Sy...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Hongyang Pan Keren Zhu Fan Yang Zhufei Chu Xuan Zeng State Key Lab of Integrated Circuits and Systems School of Microelectronics Fudan University Shanghai China Faculty of Electrical Engineering and Computer Science Ningbo University Ningbo China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Mapping to $k$ -input lookup tables ( $k$ -LUTs) is a critical process in field-programmable gate array (FPGA) synthesis. However, the structure of the subject graph can introduce structural bias, which refers to the dependency of mapping results on the inherent graph structure, often leading to suboptimal results. To address this, we present ELMap, an area-driven LUT mapping framework. It incorporates structural choice during the collapsing phase. This enables dynamic decomposition, maximizing local-to-global optimization transfer. To ensure seamless integration between the optimization and mapping processes, ELMap leverages exact $k$ -LUT synthesis to generate area-optimal sub-LUT networks. Experiments on the EPFL benchmark suite demonstrate that ELMap significantly outperforms state-of-the-art methods. Specifically, in 6-LUT mapping, ELMap reduces the average LUT area by 8.5% and improves the area-depth-product (ADP) by 5.8%. In 4-LUT remapping, it reduces the average LUT area by 17.6% and improves the ADP by 2.4%.

关键词： Europe Benchmark testing Table lookup Logic Optimization Field programmable gate arrays

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An FPGA-Based Dual-Mode SSD for Device-Side Performance Optimization 17

An FPGA-Based Dual-Mode SSD for Device-Side Performance Opti...

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17th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2024

作者： Chen, Xingyu Peng, Sirui Lv, Hankun Yang, Zhangbin Peng, Daixiao Cai, Xi Lian, Xueguang Ding, Yong Xue, Xiaoyong School of Microelectronics Fudan University State Key Laboratory of Integrated Chips and Systems Shanghai201203 China University of Chinese Academy of Sciences Beijing100049 China Institute of Electrical Engineering Chinese Academy of Sciences Beijing100190 China China Three Gorges Construction Engineering Corporation Chengdu610000 China College of Integrated Circuits Zhejiang University Hangzhou310000 China

ISBN: (纸本)9798350361834

This paper proposes a Dual-mode Solid state Drive(DM-SSD) based on FPGA that can switch modes between a traditional SSD and an open-channel SSD (OCSSD) according to users' needs. The DM-SSD is constructed through hardware and software co-design. The hardware design of the DM-SSD is mainly responsible for command fetch and data transmission while the software part is for command parsing and scheduling. Both SSD modes use the same hardware design. and users can switch the mode of SSD by flashing the firmware. Based on the traditional SSD system, the Open-Channel SSD features are added to the embedded software according to the Open-Channel SSD Specification 2.0. We have evaluated and analyzed the performance of the two SSD modes separately and comparatively. © 2024 IEEE.

关键词： Firmware

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A Semi-Tensor Product based Circuit Simulation for SAT-sweeping

A Semi-Tensor Product based Circuit Simulation for SAT-sweep...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Hongyang Pan Ruibing Zhang Yinshui Xia Lunyao Wang Fan Yang Xuan Zeng Zhufei Chu State Key Lab of Integrated Circuits and Systems School of Microelectronics Fudan University Shanghai China Faculty of Electrical Engineering and Computer Science Ningbo University Ningbo China

ISBN: (数字)9783981926385

ISBN: (纸本)9798350348606

This paper introduces a novel circuit simulator of k-input lookup table (k-LUT) networks, based on semi-tensor product (STP). STP-based simulators use computation of logic matrices, the primitives of logic networks, as opposed to relying on bitwise logic operations for simulation of k- LUT networks. Experimental results show that our STP-based simulator reduces the runtime by an average of 7.2 ×. Furthermore, we integrate this proposed simulator into a SAT sweeper. Through a combination of structural hashing, simulation, and SAT queries, SAT sweeper simplifies logic networks by systematically merging graph vertices from input to output. To enhance the efficiency, we used STP-based exhaustive simulation, which significantly reduces the number of false equivalence class candidates, thereby improving the computational efficiency by reducing the number of SAT calls required. When compared to the state-of-the-art SAT sweeper, our method demonstrates an average 35% runtime reduction.

关键词： Runtime Circuit simulation Refining Merging Table lookup Computational efficiency

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Adaptive ILT via Multi-Level Lithography Simulation

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IEEE Transactions on Computer-Aided Design of Integrated circuits and systems 2025年

作者： Sun, Shuyuan Yang, Fan Yu, Bei Shang, Li Zeng, Xuan Fudan University State Key Lab of Integrated Circuits and Systems China Fudan University School of Microelectronics China The Chinese University of Hong Kong Department of Computer Science and Engineering Hong Kong Fudan University School of Computer Science China

Inverse lithography technology (ILT) is an advanced resolution enhancement technology (RET) approach that pushes the limits of current process conditions to achieve smaller feature sizes. This paper presents an efficient ILT framework centered on the concept of solving mask optimization problem from approximation to precision. Firstly, low-resolution lithography simulation is employed to guide ILT, generating a preliminary solution at a low cost. Subsequently, high-resolution lithography simulation is utilized for fine-tuning, and output the final correction results. Additionally, we introduce a continuous correction scheme and a hyperparameter selection strategy to enhance the adaptability and robustness of the ILT solver for full-chip scale layouts. For via layer patterns, we significantly improve the solvers performance by adopting a new high-resolution ILT approach combined with a restricted optimization region. Experimental results show that our method effectively reduces edge placement error (EPE) violations and improves efficiency for ILT on full-chip scale layouts. In the ICCAD 2013 benchmark, our method outperforms state-ofthe-art approaches, reducing L2 loss by at least 1.3%. For via layer patterns, our method achieves a 98% reduction in L2 loss and nearly triples the runtime efficiency compared to its earlier version. Furthermore, it delivers an 8% reduction in L2 loss and a 45% reduction in PVBand compared to other existing methods. © 1982-2012 IEEE.

关键词： Inverse problems

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Long-term and short-term plasticity independently mimicked in highly reliable Ru-doped Ge_(2)Sb_(2)Te_(5) electronic synapses

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InfoMat 2024年第8期6卷 85-96页

作者： Qiang Wang Yachuan Wang Yankun Wang Luyue Jiang Jinyan Zhao Zhitang Song Jinshun Bi Libo Zhao Zhuangde Jiang Jutta Schwarzkopf Shengli Wu Bin Zhang Wei Ren Sannian Song Gang Niu State Key Laboratory for Manufacturing Systems Engineering Electronic Materials Research LaboratoryKey Laboratory of the Ministry of Education&International Center for Dielectric ResearchSchool of Electronic Science and EngineeringXi'an Jiaotong UniversityXi'anthe People's Republic of China School of Integrated Circuits Peking UniversityBeijingthe People's Republic of China Beijing Microelectronics Technology Institute Beijingthe People's Republic of China National Key Laboratory of Human-Machine Hybrid Augmented Intelligence National Engineering Research Center for Visual information and Applicationsand School of SoftwareXi'an Jiaotong UniversityXi'anthe People's Republic of China State Key Laboratory of Functional Materials for Informatics Shanghai Institute of Microsystem and Information TechnologyChinese Academy of SciencesShanghaithe People's Republic of China Key Laboratory of Microelectronics Device and Integrated Technology The Institute of Microelectronics of Chinese Academy of SciencesBeijingthe People's Republic of China University of Chinese Academy of Sciences Beijingthe People's Republic of China The State Key Laboratory for Manufacturing Systems Engineering&The International Joint Laboratory for Micro/Nano Manufacturing and Measurement Technology Xi'an Jiaotong UniversityXi'anthe People's Republic of China Leibniz-Institut für Kristallzüchtung Max-Born-Straße 2BerlinGermany Key Laboratory of Physical Electronics and Devices Ministry of EducationSchool of Electronic Science and EngineeringXi'an Jiaotong UniversityXi'anthe People's Republic of China The International Joint Laboratory for Micro/Nano Manufacturing and Measurement Technology Xi'an Jiaotong UniversityXi'anthe People's Republic of China

In order to fulfill the complex cognitive behaviors in neuromorphic systems with reduced peripheral circuits,the reliable electronic synapses mimicked by single device that achieves diverse long-term and short-term plasticity are *** change random access memory(PCRAM)is of great potential for artificial synapses,which faces,however,difficulty to realize short-term plasticity due to the long-lasting resistance *** work reports the ruthenium-doped Ge_(2)Sb_(2)Te_(5)(RuGST)based PCRAM,demonstrating a series of synaptic behaviors of short-term potentiation,pair-pulse facilitation,longterm depression,and short-term plasticity in the same single *** optimized RuGST electronic synapse with the high transformation temperature of hexagonal phase>380C,the outstanding endurance>108 cycles,the low resistance drift factor of 0.092,as well as the extremely high linearity with correlation coefficients of 0.999 and 0.976 in parts of potentiation and *** investigations also go insight to mechanisms of Ru doping according to thorough microstructure characterization,revealing that Ru dopant is able to enter GST lattices thus changing and stabilizing atomic arrangement of *** leads to the short-term plasticity realized by RuGST ***,the proposed RuGST electronic synapses performs a high accuracy of94.1%in a task of image recognition of CIFAR-100 database using ResNet *** work promotes the development of PCRAM platforms for large-scale neuromorphic systems.

关键词： electronic synapses neuromorphic computing PCRAM Ru-doped Ge_(2)Sb_(2)Te_(5)

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AiSpGEMM: Accelerating Imbalanced SpGEMM on FPGAs with Flexible Interconnect and Intra-row Parallel Merging

AiSpGEMM: Accelerating Imbalanced SpGEMM on FPGAs with Flexi...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Enhao Tang Shun Li Hao Zhou Guohao Dai Jun Lin Kun Wang State Key Lab of Integrated Chips & Systems School of Microelectronics Fudan University Shanghai China School of Electronic Science and Engineering Nanjing University Nanjing China School of Integrated Circuits Southeast University Nanjing China Shanghai Jiao Tong University Shanghai China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

The row-wise product algorithm shows significant potential for sparse matrix-matrix multiplication (SpGEMM) on hardware accelerators. Recent studies have made notable progress in accelerating SpGEMM using this algorithm. However, several challenges remain in accelerating imbalanced SpGEMM, where the distribution of non-zero elements across different rows is imbalanced. These challenges include: (1) the fixed dataflow of the merger tree, which leads to lower PE utilization, and (2) highly imbalanced data distributions, such as single rows with numerous non-zero elements, which result in intensive computations. This imbalance significantly challenges SpGEMM acceleration, leading to time-consuming processes that dominate overall computation time. In this paper, we propose AiSpGEMM to accelerate imbalanced SpGEMM on FPGAs. First, we improved the C 2 SR format to adapt it for imbalanced SpGEMM acceleration based on the row-wise product algorithm. This reduces off-chip memory bank conflicts and increases data reuse of matrix B. Secondly, we design a reconfigurable merger (R-merger) with flexible interconnects to improve PE utilization. Additionally, we propose an intra-row parallel merging algorithm and its corresponding hardware architecture, the parallel merger (P-merger), to accelerate intensive operations. Experimental results demonstrate that AiSpGEMM achieves a geometric mean (geomean) speedup of 5.8× compared to the state-of-the-art FPGA-based SpGEMM accelerator. In Geomean, AiSpGEMM achieves a 3.0× speedup and a 9.8× improvement in energy efficiency compared to the NVIDIA cuSPARSE library running on an NVIDIA A6000 GPU. Moreover, AiSpGEMM-21 demonstrated a 4× increase in average throughput compared to the same GPU.

关键词： Corporate acquisitions Merging Graphics processing units Performance gain Parallel processing Throughput Libraries Energy efficiency Sparse matrices Field programmable gate arrays

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