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EUROSOI Workshop and International Conference on Ultimate Integration on Silicon

作者： Sabina Krivec Mirko Poljak Tomislav Suligoj Department of Electronics Microelectronics Computer and Intelligent Systems Faculty of Electrical Engineering and Computing University of Zagreb HR-10000 Croatia

ISBN: (纸本)9781509053148

The impact of strain on the electron mobility is investigated in ultra-thin InGaAs-OI channels by combining tight-binding bandstructure simulations, self-consistent Schrodinger-Poisson, and mobility simulations including all relevant scattering mechanisms. Our model shows that strain induced mobility improvement increases with body thickness downscaling, up to 164% in 4 nm-thick InGaAs channels in strong inversion.

关键词： InGaAs-OI electron mobility strain Fermi level pinning interface charge ultra-thin body

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Impact of different gate insulator materials on the electron mobility in ultra-thin (100) InGaAs-on-insulator MOS devices

Impact of different gate insulator materials on the electron...

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Proceedings of the International Convention MIPRO

作者： Sabina Krivec Mirko Poljak Tomislav Suligoj Department of Electronics Microelectronics Computer and Intelligent Systems University of Zagreb Zagreb Croatia

In this paper, we studied the influence of the parameters of technologically relevant dielectrics (SiO 2 , Al 2 O 3 and HfO 2 ) and channel thickness downscaling on the electron mobility in InGaAs-on-insulator channels with (100) surface orientation. The study of mobility properties is enabled by a self-consistent Schrödinger-Poisson solver that is coupled with a scattering simulator based on the momentum relaxation time approximation, in order to calculate the scattering rates of electrons with acoustic, optical, remote and polar phonons, surface roughness, Coulomb impurities and alloy disorder. Simulations revealed that SiO 2 is the optimum gate dielectric material irrespective of the body thickness, followed by Al 2 O 3 or HfO 2 , depending on InGaAs-to-oxide surface roughness.

关键词： Logic gates Scattering Aluminum oxide Dielectrics Hafnium compounds Electron mobility Rough surfaces

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On the enhancement of electron mobility in ultra-thin (111)-oriented In0.53Ga0.47As channels

On the enhancement of electron mobility in ultra-thin (111)-...

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International Conference on Ultimate Integration of Silicon, ULIS

作者： Mirko Poljak Sabina Krivec Tomislav Suligoj Department of Electronics Microelectronics Computer and Intelligent Systems University of Zagreb Zagreb Croatia

Electron mobility is investigated in sub-20 nm-thick InGaAs channels using self-consistent numerical simulations. Effects of body thickness downscaling [down to 2 nm] and surface orientation [(100) and (111)] are examined by including all electron valleys and all relevant scattering mechanisms. We report that ultra-thin (111) InGaAs channels offer greater electron mobility than (100) devices down to 2 nm. Furthermore, ultra-thin (100) InGaAs devices outperform SOI for body thicknesses above 3.2 nm, while (111) InGaAs channels are superior to SOI irrespective of the body thickness.

关键词： Indium gallium arsenide Scattering Electron mobility MOSFET Rough surfaces Surface roughness

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Optimization of floating guard ring parameters in separate-absorption-and-multiplication silicon avalanche photodiode structure

Optimization of floating guard ring parameters in separate-a...

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Proceedings of the International Convention MIPRO

作者： I. Janeković T. Knežević T. Suligoj D. Grubišić Department of Electronics Microelectronics Computer and Intelligent Systems University of Zagreb Croatia Laser Components DG Inc. Tempe Arizona USA

In this paper, the effect of the floating guard ring (FGR) parameters, such as number of FGRs and the distances between the FGRs, on the prevention of the breakdown at the multiplication layer edge for a given avalanche photodiode (APD) structure has been analyzed. Four structures are examined: APD without FGR and APDs with one, two and three FGRs. The width and depth of the boron-doped FGRs is 1 μm with peak concentration of 1018 cm -3 . The intrinsic breakdown voltage in the active region of the APD is 371 V and the epitaxial layer is fully depleted at 14 V. The breakdown occurs in the active area of the APD structure by using three FGRs. The optimal position of three FGRs are determined and the breakdown voltage of 409 V is achieved at the multiplication edge, which is higher by 38 V than in the active region. In contrast, the edge breakdown voltage is 170 V, 270 V and 348 V for structures without floating guard rings, with one FGR and with two FGRs, respectively. Spectral responsivity of the structure is analyzed in the range of 400 to 1000 nm showing that such APD can be effectively used for detection of the visible light.

关键词： Electric fields Electric breakdown Impact ionization Semiconductor process modeling Structural rings Avalanche photodiodes Silicon

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Multi-level image annotation using Bayes classifier and fuzzy knowledge representation scheme

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WSEAS Transactions on computers 2014年 13卷 635-644页

作者： Ivasic-Kos, Marina Ipsic, Ivo Ribaric, Slobodan Department of Informatics University of Rijeka R. Matejčić 2 Rijeka51000 Croatia Department of Electronics Microelectronics Computer and Intelligent Systems Faculty of Electrical Engineering and Computing University of Zagreb Unska 3 Zagreb10000 Croatia

Automatic image annotation (AIA) is the process by which metadata, in form of keywords or text descriptions are automatically assigned to an unlabeled image. Generally, two problems can be distinguished: the problem of semantic extraction, due to the gap between the image features and object labels, and the problem of semantic interpretation, due to the gap between the object labels and the human interpretation of images. In this paper, a model for multi-level image annotation that is performed in two phases is proposed. In the first phase, a Naïve Bayes classifier is used to classify low-level image features into elementary classes. In the second phase, a knowledge representation scheme based on Fuzzy Petri Net is used to expand the level of vocabulary and to include multi-level semantic concepts related to images into image annotations. In the paper, a knowledge representation scheme for outdoor image annotation is given. Procedures for determining concepts related to an image using fuzzy recognition and inheritance algorithms on a knowledge representation scheme are presented, as well as experimental results of image annotation.

关键词： Image annotation

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Comparison of RF performance between 20 nm-gate bulk and SOI FinFET

Comparison of RF performance between 20 nm-gate bulk and SOI...

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Proceedings of the International Convention MIPRO

作者： S. Krivec H. Prgić M. Poljak T. Suligoj Department of Electronics Microelectronics Computer and Intelligent Systems University of Zagreb Zagreb Croatia

Due to their 3D architecture, FinFETs exhibit a strong dependence of RF figures-of-merit on device geometry due to large extrinsic resistances and capacitances. We analyze the RF performance of 20-nm gate length FinFETs implemented on either bulk or SOI substrate by using 3D numerical device simulation. SOI and bulk FinFET are compared in terms of cut-off and maximum oscillation frequency, gate capacitance and trans-conductance. We have proposed and investigated the influence of different doping methods that aim at improving the RF figures-of-merit of 20 nm bulk FinFETs while maintaining acceptable DC performance.

关键词： FinFETs Logic gates Capacitance Cutoff frequency Radio frequency Gain Transconductance

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Impact of control flow blocks granularity on custom processor design time

Impact of control flow blocks granularity on custom processo...

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Proceedings of the International Convention MIPRO

作者： D. Ivošević V. Sruk Department of Electronics Microelectronics Computer and Intelligent Systems Faculty of Electrical Engineering and Computing Zagreb Croatia

One of the key issues for system level design topic is the design time. This paper describes custom processor design tool as part of C-to-hardware flow and analyses its design time. The flow starts with C code specification and ends with FPGA implementation. The way the C code is processed has impact on the flow execution time. The implemented C code processing results with Control Flow Graph (CFG), and large control flow code blocks severely prolong the overall design time. Between two possibilities for design time improvement, variations in their granularities are chosen over tool internal algorithm and data structures optimizations. For 32-point DCT test case the results show huge design time decrease at the expense on the design quality: implementation resource occupation and execution time.

关键词： Discrete cosine transforms Field programmable gate arrays Registers Algorithm design and analysis computer architecture Optimization Schedules

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Extension and Detailed Overview of the HRVFrame Framework for Heart Rate Variability Analysis

Extension and Detailed Overview of the HRVFrame Framework fo...

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IEEE EUROCON

作者： Alan Jovic Nikola Bogunovic Marko Cupic Department of Electronics Microelectronics Computer and Intelligent Systems Faculty of Electrical Engineering and Computing University of Zagreb

ISBN: (纸本)9781467322331

The analysis of heart rate variability (HRV) is an important diagnostic method for detection and assessment of cardiac abnormalities. The availability of complete computer frameworks that can aid researchers in the field of HRV analysis is limited due to the large number of different feature extraction methods. A recently developed framework for feature extraction from cardiac rhythm called HRVFrame is promising, because it allows a user to access more than 40 implemented linear and nonlinear methods. The aim of this paper is to provide a more detailed overview of this framework and all of its capabilities and recent extensions. Additionally, the aim is to encourage the use of HRVFrame as a free and open-source tool for developing medical applications based on Java programming language. A comparison of the framework with existing solutions for cardiac rhythm analysis is provided.

关键词： Feature extraction Heart rate variability Framework Java programming Open-source software Medical applications

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Unified Flow of Custom Processor Design and FPGA Implementation

Unified Flow of Custom Processor Design and FPGA Implementat...

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IEEE EUROCON

作者： Danko Ivosevic Vlado Sruk Faculty of Electrical Engineering and Computing University of Zagreb Department of Electronics Microelectronics Intelligent and Computer Systems

ISBN: (纸本)9781467322331

The automation of custom hardware design often focuses on hardware optimizations for smaller portions of code that dominate the design execution. The same presumption can be stated for custom processor design. The data path of the processor can be well optimized for particular blocks of code that are formed during control flow extraction. However, larger source codes can have tens of blocks that result from Control Flow Graph (CFG). We implemented a global semi-automated flow that hierarchically forms the set of blocks which contributions are modeled into processor architecture. Resulting processor model is translated to RTL description and implemented inside FPGA logic.

关键词： Custom Processor Design No-Instruction-Set computer High-Level Synthesis Data Path Design FPGA Implementation

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Feature extraction from electroencephalographic records using EEGFrame framework

Feature extraction from electroencephalographic records usin...

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Proceedings of the International Convention MIPRO

作者： Alan Jović Lea Suć Nikola Bogunović Faculty of Electrical Engineering and Computing Department of Electronics Microelectronics Computer and Intelligent Systems University of Zagreb Zagreb Croatia

Analysis of electroencephalographic (EEG) signals usually includes visual inspection of the signal, feature extraction, and model generation. computer-aided nonlinear feature extraction from EEG in particular has already led to improved descriptive and prognostic models of brain states and disorders. However, in this field, there is a lack of freely available powerful tools for scientific exploration of EEG that would help researchers to compare the results of their work with others. Especially, because of the great diversity of the proposed methods for EEG analysis, there exists a need for a joint framework for inspection, extraction and visualization performed on the EEG records. The aim of this paper is to introduce such a framework, called EEGFrame, with its implementation in Java. The framework currently supports the analysis of standard EDF records via signal inspection, feature extraction, and feature vectors storage for knowledge discovery. EEGFrame is the result of refactoring and extension of the HRVFrame framework for heart rate variability analysis, with added methods for EEG analysis. This paper describes the properties and capabilities of the framework and discusses its relevance with respect to similar work. The main advantage of EEGFrame is its support for numerous linear and nonlinear methods described in literature.

关键词： Feature extraction Electroencephalography Entropy Brain modeling MATLAB Visualization

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