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检索条件"机构=Microelectronics Computer and Intelligent Systems"

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Evaluation of embedded processor based BDD implementation

Evaluation of embedded processor based BDD implementation

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Proceedings of the International Convention MIPRO

作者： Danko Ivošević Vlado Sruk Department of Electronics Microelectronics Computer and Intelligent Systems University of Zagreb Zagreb Croatia

Different strategies for implementation of computationally intensive applications in hardware are available today. The spectrum of implementations ranges from usage of standardized microprocessors to specially tailored hardware solutions. Available processor architectures range from general purpose type through processors with instruction set extensions to application-specific processors. On the other side, recent advances in design automation resulted in development of C-to-hardware compilers as a new strategy for application implementation in hardware. In this paper, we present and elaborate characteristics of hardware implementations of Binary Decision Diagrams (BDDs) application, used in many research and development areas, and especially in formal verification and computer-Aided Design (CAD) tools. For this application, processor architecture using C-to-hardware NISC toolset is manually tailored and compared with implementation approaches based on standard soft and hard processors. All these approaches are implemented and verified using FPGA Virtex-5 development board. Our results show that, besides code and compiler side optimizations, more significant improvements in total execution cycles count can be achieved when processor architecture side optimizations are included.

关键词： Binary decision diagrams Hardware Design automation Application software Optimizing compilers computer applications Microprocessors Application specific processors Data structures Boolean functions

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Quantum-mechanical modeling of phonon-limited electron mobility in bulk MOSFETs, ultrathin-body SOI MOSFETs and double-gate MOSFETs for different orientations

Quantum-mechanical modeling of phonon-limited electron mobil...

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33rd International Convention on Information and Communication Technology, Electronics and microelectronics, MIPRO 2010

作者： Poljak, M. Jovanović, V. Suligoj, T. Department of Electronics Microelectronics Computer and Intelligent Systems Faculty of Electrical Engineering and Computing University of Zagreb Unska 3 HR-10000 Zagreb Croatia ECTM-DIMES Delft University of Technology Feldmannwed 17 2628 CT Delft Netherlands

ISBN: (纸本)9789532330502

A comprehensive study of low-field phonon-limited mobility behavior with downscaling of silicon body thickness in ultrathin-body SOI MOSFETs and double-gate MOSFETs is presented. Phonon-limited mobility is obtained by self-consistent Schrödinger-Poisson simulations and momentum relaxation rate calculations. Single- and double-gate devices with (100), (110) and (111) active surfaces and body thickness down to 2 nm are investigated. Physical mechanisms which govern mobility behavior are studied by calculating form factors and ladder/subband occupancy.

关键词： Quantum theory

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computer cluster workload analysis

Computer cluster workload analysis

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Proceedings of the International Convention MIPRO

作者： I. Grudenic I. Bakarcic N. Bogunovic Department of Electronics Microelectronics Computer and Intelligent Systems Faculty of electrical engineering and computing University of Zagreb Zagreb Croatia

Performance of computer clusters is greatly affected by a nature of the submitted workload. Early characterization of different workload types allows for scheduler fine tuning as well as predictions on the system load. Statistical analysis and visual representation of the workload data provide valuable insight to the overall system utilization and may reveal potential bottlenecks and points for improvement. In this paper we describe important cluster job features and introduce a tool for statistical analysis and manipulation of the workload data that is a part of a cluster simulation and runtime prediction system.

关键词： Analytical models Processor scheduling Job shop scheduling Computational modeling Runtime Predictive models Data mining Statistical analysis computer architecture computer simulation

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Image annotation using fuzzy knowledge representation scheme

Image annotation using fuzzy knowledge representation scheme

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International Conference of Soft Computing and Pattern Recognition (SOCPAR)

作者： Marina Ivasic-Kos Ivo Ipsic Slobodan Ribaric Department of Informatics University of Rijeka Rijeka Croatia Department of Electronics Microelectronics Computer and Intelligent Systems University of Zagreb Zagreb Croatia

In order to exploit the massive image information and to handle overload, techniques for analysing image content to facilitate indexing and retrieval of images have emerged. In this paper, a semantic image content analysis framework based on Fuzzy Petri Net is presented. Knowledge scheme is used to define more general and complex semantic concepts and their relations in the context of the examined outdoor domain. A formal description of hierarchical and spatial relationships among concepts from the outdoor image domain is described. The automatic image annotation procedure based on fuzzy recognition algorithm, that maps high-level semantics to image, is presented.

关键词： Semantics Image segmentation Knowledge based systems Firing Image recognition Classification algorithms Knowledge representation

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Quantum-mechanical modeling of phonon-limited electron mobility in bulk MOSFETs, ultrathin-body SOI MOSFETs and double-gate MOSFETs for different orientations

Quantum-mechanical modeling of phonon-limited electron mobil...

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Proceedings of the International Convention MIPRO

作者： M. Poljak V. Jovanović T. Suligoj Department of Electronics Microelectronics Computer and Intelligent Systems University of Zagreb Zagreb Croatia ECTM-DIMES Delft University of Technology Delft The Netherlands

关键词： MOSFETs Electron mobility Optical scattering Acoustic scattering Particle scattering Poisson equations Silicon Quantum computing Phonons Schrodinger equation

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Classification of Biological Signals Based on Nonlinear Features

Classification of Biological Signals Based on Nonlinear Feat...

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IEEE Mediterranean Electrotechnical Conference

作者： Alan Jovic Nikola Bogunovic Department of Electronics Microelectronics Intelligent and Computer Systems Faculty of Electrical Engineering and Computing University of Zagreb

ISBN: (纸本)9781424457939

The problem of patient disorder classification and prediction from biological signals is addressed. We approach the problem from the perspective of nonlinear dynamical systems. Explored signals are ECG and EEG. We propose a combination of linear and nonlinear features for classification of four different types of heart rhythms through heart rate variability analysis. Classification accuracy is evaluated by three well-known machine learning algorithms: C4.5, support vector machines and random forest. The algorithms' success rates are compared. The method of combining linear and nonlinear measures shows promising results in heart rate variability modeling. Random forest method has exhibited 99.6% classification accuracy.

关键词： Cardiac Rhythm signals heart rate variability Nonlinear dynamical systems nonlinearity electrocardiograph and electroencephalograph disorder classification Taxonomy Biological Perspective

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Power MOS transistors integrated in standard CMOS technology without any increase in process complexity

Power MOS transistors integrated in standard CMOS technology...

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32nd International Convention Proceedings: microelectronics, Electronics and Electronic Technology, MEET and Grid and Visualizations systems, GVS

作者： Šarlija, M. Vasiljević, I. Suligoj, T. Department of Electronics Microelectronics Computer and Intelligent Systems University of Zagreb Unska 3 Zagreb Croatia

ISBN: (纸本)9789532330441

In this paper, we developed power MOS structures where the drift region is fabricated by using the process steps that already exist in CMOS baseline technology, such as, LDD and/or n-well region together with LOCOS isolation and p+ implantation. Five different structures fabricated in a standard 0.35μm CMOS technology are examined by measurements and simulations and the effect of various technology parameters on device characteristics are analyzed. The optimum power MOS structure has BVDS=20V, RON=9.4kΩμm and ION=220μA/μm, which correspond to the changes of +203%, +213% and -46%, respectively, comparing to standard nMOS transistor. © 2009 by MIPRO.

关键词： Structural optimization

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computer cluster and grid simulator

Computer cluster and grid simulator

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32nd International Convention Proceedings: computers in Technical systems and intelligent systems

作者： Grudenic, I. Bogunovic, N. Department of Electronics Microelectronics Computer and Intelligent Systems University of Zagreb Unska 3 Zagreb Croatia

ISBN: (纸本)9789532330458

Evaluation of scheduling algorithms for distributed environments is a complex task that involves simulation of computation resources, interconnection network, users and generated workload. Multiple discrete event based simulators are developed that tackle different aspects of distributed systems in order to ease that task. In this paper we address the simulation of computer clusters that are the most popular distributed system architecture. Fundamentals of the available simulators are given and the extendable architecture for the new simulator is proposed. Three-phase discrete event simulation is recognized as the simulation technique of choice, and the behavior of the key components is modeled using that technique. Implementation details targeted to object oriented environments are pointed out. © 2009 by MIPRO.

关键词： Discrete event simulation

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WISHBONE bus interface for the no-instruction-set computer (NISC)

WISHBONE bus interface for the no-instruction-set computer (...

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32nd International Convention Proceedings: computers in Technical systems and intelligent systems

作者： Grubišić, Roko Sruk, Vlado Department of Electronics Microelectronics Computer and Intelligent Systems University of Zagreb Unska 3 10000 Zagreb Croatia

ISBN: (纸本)9789532330458

General-purpose processors are often unable to effectively exploit the parallelism inherent to the software code. In such cases, additional hardware accelerators are needed to enable meeting the performance goals. To shorten time to market and enable meeting design constraints, designers today use special tools and technologies like the No- Instruction-Set computer (NISC) to automatically generate custom accelerators. However, it is often difficult to integrate these accelerators into general-purpose processor systems and use them from the main processor's software. In this paper we present a simple and efficient method for using the NISC processor as a loosely-coupled coprocessor. To enable communication with the NISC processor, a simple set of coprocessor services exposed to the application programmer is defined. A hardware solution based on standard SoC bus architectures for implementing these services is described. Using a standard SoC bus interface enables simple integration of the NISC design flow into an existing design flow. A practical implementation of the NISC coprocessor WISHBONE interface was realized and tested in a system based on a WISHBONE-compatible general-purpose soft processor. © 2009 by MIPRO.

关键词： Coprocessor

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Design space exploration of a multi-core JPEG

Design space exploration of a multi-core JPEG

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32nd International Convention Proceedings: computers in Technical systems and intelligent systems

作者： Zadrija, V. Sruk, V. Department of Electronics Microelectronics Computer and Intelligent Systems University of Zagreb Unska 3 Zagreb 10000 Croatia

ISBN: (纸本)9789532330458

This paper presents the design space exploration of a multi-core implementation of the JPEG algorithm using the Embedded System Environment (ESE). ESE is a tool-set, which enables multi-core system design by high-level modeling of both the hardware platform and software application. In order to define an application model for ESE, sequential JPEG code written in C was partitioned and translated into concurrent processes, which communicate via abstract channels. The application model is then mapped on the system platform captured as a graphical netlist consisted out of SW and HW cores, buses and buffers. ESE provides means for automatic translation of these models to Transaction Level Models (TLM) in order of seconds. Highspeed TLM simulation was used to identify possible bottlenecks and evaluate different design options for both HW and SW partitioning of the JPEG algorithm application. The obtained experimental results have shown that such approach may find a good solution regarding specific design constraints in a very short time. © 2009 by MIPRO.

关键词： C (programming language)

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